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S5T8809 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 S5T8809은 전자 산업 및 응용 분야에서
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부품번호 S5T8809 기능
기능 PLL FREQUENCY SYNTHESIZER FOR PAGER
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S5T8809 데이터시트, 핀배열, 회로
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
INTRODUCTION
S5T8809 is a superior low-power-programmable PLL frequency
synthesizer which can be used in high performance / Simple
application for a Wide Area Pager system.
S5T8809 consists of 2 kinds of divider block including a 19-bit Shift
register, 16/18-bit Latch, 13/15bits R-counter and 16/18-bit N-
Counter, 32/33 Prescaler, and a phase detector block including a
Phase detector, Lock detector and a Charge pump.
S5T8809 also has a battery saving mode which can control each
register block by serial control data from the µ-controller (MICOM)
and it also has boost up signal output for fast locking.
16-TSSOP-0044
( Magnification = 1 : 4 )
FEATURES
• Maximum operating frequency: 330MHz @ 300mVP-P, VDD1 = 1.0V, VDD2 = 3.0V
• On-chip reference oscillator supports external crystal which oscillates up to 23MHz
• Superior supply current:
— FFIN = 310MHz, IDD1 = 0.8mA (Typ.) @ VDD1 = 1.0V, VDD2 = 3.0V
• Operating voltage: VDD1 = 0.95 to 1.5V and VDD2 = 2.0 to 3.3V
• Excellent Divider range:
— Ref. Divider:
FRC (0): 1 / 40 to 1 / 65528 (Multiple): Default
FRC (1): 1 / 5 to 1 / 32767
— Rx Divider:
PBC (0): 1 / 1056 ~ 1 / 65535: Default
PBC (1): 1 / 1056 ~ 1 / 262143
• Boost-up signal output for Fast Locking
• In the Standby mode, VDD1 block can be controlled by BSB Pin status
— Standby current consumption: 10µA (Max.)
• Programmable control the output of LD to reduce internal noise
• Programmable 17 / 19-bit shift register value controlled by PBC
• Charge pump output circuitry for passive filter
• Package type: 16TSSOP (0.65mm)
ORDERING INFORMATION
Device
+S5T8809X01-R0B0
+: New Product
Package
16TSSOP0044
Operating Temperature
25°C to +75°C
1




S5T8809 pdf, 반도체, 판매, 대치품
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGE
PIN DESCRIPTION
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
OSCI
OSCO
VDD2
FL
PDO
VSS
Fin
VDD1
PBC
LD
CLK
DATA
EN
BSB
FLC
TEST
Description
These input / output pins generate the reference frequency.
In case of OSCI Pin, external reference frequency can be used through the AC coupling.
The highest potential supply terminal that can be supplied up to 2.0 ~ 3.3V.
Booster signal output for fast locking.
The output of RX phase detector terminal for passive loop filter.
There are 3-kinds of output signal states according to Rx loop error.
Ground terminal
Input terminal for the frequency from VCO.
Output frequency from VCO was inputted through AC coupling
Voltage supply terminal for Oscillator and Fin block.
This pin can be supplied up to 0.95 ~ 1.5V from VSS.
This is an input for programmable bit control which has Schmitt Trigger architecture,
Internally biased pull-up.
High = 16 Bits N-Divider (Default: ND0 ~ ND15)
Low = 18 Bits N-Divider (ND0 ~ ND7)
cf) R-divider bits will be changed by the FRC bit of program
The output of phase detector can be controlled by R-counter register. When the LDC bit
of R-counter set to Low, the output will be disabled to reduce a noise problem, but if it is
set to High, the output will be enabled to show an lock / unlock status that is the error
width between to Ref. signal and the VCO output signal.
These pins are controlled by the µ-controller which has Schmitt Trigger architecture,
Internally biased pull-down. The features of these pins are as follows; Clock input for 17
or 19-bit Shift Register, Serial data input (it include TEST1, FRC and LDC), and Latch
enable input.
In the BS mode (set to Low), the VDD1 block will be powered off, but the internal latch
data is still valid because the VDD2 is supplied continuously. This input has Schmitt
Trigger architecture & internally biased pull-up.
This is the input pin for Fast Locking Control (FLC) which has Schmitt Trigger
architecture, Internally biased pull-down.
Low = The Current of PDO Charge pump output is Normal (Default: x1)
High = The Current of PDO Charge pump output is increase (x 1.5)
This is the input pin for TEST which has Schmitt trigger architecture, Internally biased
Pull-down.
Low = All block will be operated as normal state (Default)
High = LD and FL state will be TES mode
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S5T8809 전자부품, 판매, 대치품
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
• Ex 1) In case of 16-bits program [PBC = High], Fc = 325.300MHz, Multiplier = 4, Fin = 75.975MHz
[Fin Freq. / Ref. Frequ.] = 75.975MHz / 6.25kHz = 1256
210
20 25
20
00101111101111000
MSB
LSB
Main CNT 11 - bits
Swallow CNT 5-bits PMC bit
NOTE: According to the above equation, 12156 / 32(P) = 379, and left = 28
that means, Swallow CNT value is 11100, Main CNT value is 379
• Ex 2) In case of 18-bits program [PBC = Low], Fin = 330MHz
[Fin Freq. / Ref. Freq.] = [330MHz / 6.25kHz] = 52800
2 217 10
20 25
20
0011001110010000000
MSB
LSB
Main CNT 13 - bits
Swallow CNT 5-bits PMC bit
NOTE: The PMC bit is program mode control bit, if [0], the N-counter will be enabled
Table 2. R-Counter Register Program Scheme (19 bits)
Bit
Bit 18 ~ Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Name
RD
LDC
FRC
TEST 1
PMC
Description Ref. R-Counter Data
Lock Detector Frequency of
Control
Reference
Control
TEST mode Program mode
control
control
Function
15 Bit Programmable
0: Disable
Ref. R-Counter
LD out
FRC = 0 : 13 bits (RD12 — RD0) 1: Enable
FRC = 1 : 15 bits (RD14 — RD0) LD out
0: R_CNT div.
= 8 × RD
1: R_CNT div.
= RD (15bit)
Mainly for
the product
Test
0: ND Program
1: RD Program
• The Input Reference Frequency (X-tal Oscillator) will be divided by 1/8 Prescaler, and then divided by pre-
programmed R-counter value once more.
• Programmable R-Counter consists of Fixed 1/8 Prescaler, 13 / 15-bits Programmable Counter
When FRC = 0, Fixed 1/8 Prescaler and 13-bits counter (Min. Divide value: 5) are enabled
RD = 8, R = 40 (= 8 × 5) ~ 65528 [Multiple 8]
When FRC = 1, Fixed 1/8 Prescaler is disabled, but using 15-bits counter (Min. Divide value: 5)
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