|
|
PDF IS24C256-2P Data sheet ( Hoja de datos )
| Número de pieza | IS24C256-2P | |
| Descripción | 262/144-bit 2-WIRE SERIAL CMOS EEPROM | |
| Fabricantes | ETC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IS24C256-2P (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
IS24C256
262,144-bit 2-WIRE SERIAL
CMOS EEPROM
FEATURES
• Organization:
– 32K-bit x 8-bit
• 64-Byte Page Write Buffer
• Two-Wire Serial Interface
– Bi-directional data transfer protocol
• Low Power CMOS Technology
– Active Current less than 3 mA (5V)
– Standby Current less than 6 µA (5V)
– Standby Current less than 2 µA (2.5V)
• Wide Voltage Operation
– IS24C256-2: Vcc = 1.8V to 5.5V
– IS24C256-3: Vcc = 2.5V to 5.5V
• 1 MHz (I2CTM Protocol) Compatibility
• Hardware Data Protection
– Write Protect pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time Write cycle with auto clear
– 5 ms @ 5.0V
• High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 40 Years
• Commercial and Industrial temperature ranges
• 8-pin PDIP, 8-pin SOIC, and 14-pin TSSOP
ISSI®
DESCRIPTION
ADVANCED INFORMATION
MARCH 2003
The IS24C256 is an electrically erasable PROM device
that uses the standard 2-wire interface for
communications. The IS24C256 contains a memory
array of 256K-bits (32,768 x 8), and is further
subdivided into 512 pages of 64 bytes each for Page-
Write mode. This EEPROM is offered in wide operating
voltages of 1.8V to 5.5V (IS24C256-2) and 2.5V to 5.5V
(IS24C256-3) to be compatible with most application
voltages. ISSI designed the IS24C256 to be a low-cost
and low-power 2-wire EEPROM solution. The devices
are packaged in 8-pin PDIP, 8-pin SOIC, and 14-pin
TSSOP.
The IS24C256 maintains compatibility with the popular
2-wire bus protocol, so it is easy to design into
applications implementing this bus type. The simple
bus consists of the Serial Clock wire (SCL) and the
Serial Data wire (SDA). Using the bus, a Master device
such as a microcontroller is usually connected to one
or more Slave devices such as the IS24C256. The bit
stream over the SDA line includes a series of bytes,
which identifies a particular Slave device, an
instruction, an address within that Slave device, and a
series of data, if appropriate. The IS24C256 has a Write
Protect pin (WP) to allow blocking of any write
instruction transmitted over the bus.
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00B
03/11/03
1
1 page  
IS24C256
ISSI®
Page Write
The IS24C256 is capable of64-byte Page-Write operation. A
Page-Write is initiated in the same manner as a Byte Write,
but instead of terminating the internal Write cycle after the
first data word is transferred, the Master device can transmit
up to 63 more bytes. After the receipt of each data word, the
IS24C256 responds immediately with an ACK on SDA line,
and the six lower order data word address bits are internally
incremented by one, while the higher order bits of the data
word address remain constant. If the Master device should
transmit more than 64 words, prior to issuing the Stop
condition, the address counter will “roll over,” and the previously
written data will be overwritten. Once all 64 bytes are
received and the Stop condition has been sent by the Master,
the internal programming cycle begins. At this point, all
received data is written to the IS24C256 in a single Write
cycle. All inputs are disabled until completion of the internal
Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition
is issued to indicate the end of the host's Write operation,
the IS24C256 initiates the internal Write cycle. ACK
polling can be initiated immediately. This involves issuing
the Start condition followed by the Slave address for a
Write operation. If the IS24C256 is still busy with the Write
operation, no ACK will be returned. If the IS24C256 has
completed the Write operation, an ACK will be returned
and the host can then proceed with the next Read or Write
operation.
READ OPERATION
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address
is set to “1”. There are three Read operation options:
current address read, random address read, and sequential
read.
Current Address Read
The IS24C256 contains an internal address counter which
maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation
is either a Read or Write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the IS24C256
receives the Device Addressing Byte with a Read operation
(R/W bit set to “1”), it will respond an ACK and transmit the
8-bit data word stored at address location n+1. The
Master should not acknowledge the transfer but should
generate a Stop condition so the IS24C256 discontinues
transmission. If 'n' is the last byte of the memory, then the
data from location '0' will be transmitted. (Refer to
Figure 8. Current Address Read Diagram.)
Random Address Read
Selective Read operations allow the Master device to
select at random any memory location for a Read
operation. The Master device first performs a 'dummy'
Write operation by sending the Start condition, Slave
address and word address of the location it wishes to
read. After the IS24C256 acknowledges the word address,
the Master device resends the Start condition and the
Slave address, this time with the R/W bit set to one. The
IS24C256 then responds with its ACK and sends the data
requested. The Master device does not send an ACK but
will generate a Stop condition. (Refer to Figure 9. Random
Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS24C256 sends initial byte sequence, the Master device
now responds with an ACK indicating it requires additional
data from the IS24C256. The IS24C256 continues to
output data for each ACK received. The Master device
terminates the sequential Read operation by pulling SDA
High (no ACK) indicating the last data word to be read,
followed by a Stop condition.
The data output is sequential, with the data from address
n followed by the data from address n+1, ... etc. The
address counter increments by one automatically, allowing
the entire memory contents to be serially read during
sequential Read operation. When the memory address
boundary 32767 is reached, the address counter “rolls
over” to address 0, and the IS24C256 continues to output
data for each ACK received. (Refer to Figure 10. Sequential
Read Operation Starting with a Random Address Read
Diagram.)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
03/11/03
5
5 Page 
IS24C256
AC WAVEFORMS
Figure 11. Bus Timing
SCL
SDAIN
SDAOUT
tR
tF
tHIGH
tLOW
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tAA tDH
WP
ISSI®
tSU:STO
tBUF
tSU:WP
tHD:WP
Figure 12. Write Cycle Timing
SCL
SDA
8th BIT
WORD n
ACK
STOP
Condition
tWR
START
Condition
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
03/11/03
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet IS24C256-2P.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IS24C256-2G | 262/144-bit 2-WIRE SERIAL CMOS EEPROM | ETC |
| IS24C256-2GI | 262/144-bit 2-WIRE SERIAL CMOS EEPROM | ETC |
| IS24C256-2P | 262/144-bit 2-WIRE SERIAL CMOS EEPROM | ETC |
| IS24C256-2PI | 262/144-bit 2-WIRE SERIAL CMOS EEPROM | ETC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |