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IS24C256-3ZI 데이터시트 PDF




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부품번호 IS24C256-3ZI 기능
기능 262/144-bit 2-WIRE SERIAL CMOS EEPROM
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IS24C256-3ZI 데이터시트, 핀배열, 회로
IS24C256
262,144-bit 2-WIRE SERIAL
CMOS EEPROM
FEATURES
• Organization:
– 32K-bit x 8-bit
• 64-Byte Page Write Buffer
• Two-Wire Serial Interface
– Bi-directional data transfer protocol
• Low Power CMOS Technology
– Active Current less than 3 mA (5V)
– Standby Current less than 6 µA (5V)
– Standby Current less than 2 µA (2.5V)
• Wide Voltage Operation
– IS24C256-2: Vcc = 1.8V to 5.5V
– IS24C256-3: Vcc = 2.5V to 5.5V
• 1 MHz (I2CTM Protocol) Compatibility
• Hardware Data Protection
– Write Protect pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time Write cycle with auto clear
– 5 ms @ 5.0V
• High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 40 Years
• Commercial and Industrial temperature ranges
• 8-pin PDIP, 8-pin SOIC, and 14-pin TSSOP
ISSI®
DESCRIPTION
ADVANCED INFORMATION
MARCH 2003
The IS24C256 is an electrically erasable PROM device
that uses the standard 2-wire interface for
communications. The IS24C256 contains a memory
array of 256K-bits (32,768 x 8), and is further
subdivided into 512 pages of 64 bytes each for Page-
Write mode. This EEPROM is offered in wide operating
voltages of 1.8V to 5.5V (IS24C256-2) and 2.5V to 5.5V
(IS24C256-3) to be compatible with most application
voltages. ISSI designed the IS24C256 to be a low-cost
and low-power 2-wire EEPROM solution. The devices
are packaged in 8-pin PDIP, 8-pin SOIC, and 14-pin
TSSOP.
The IS24C256 maintains compatibility with the popular
2-wire bus protocol, so it is easy to design into
applications implementing this bus type. The simple
bus consists of the Serial Clock wire (SCL) and the
Serial Data wire (SDA). Using the bus, a Master device
such as a microcontroller is usually connected to one
or more Slave devices such as the IS24C256. The bit
stream over the SDA line includes a series of bytes,
which identifies a particular Slave device, an
instruction, an address within that Slave device, and a
series of data, if appropriate. The IS24C256 has a Write
Protect pin (WP) to allow blocking of any write
instruction transmitted over the bus.
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00B
03/11/03
1




IS24C256-3ZI pdf, 반도체, 판매, 대치품
IS24C256
ISSI®
DEVICE OPERATION
The IS24C256 features a serial communication and
supports a bi-directional 2-wire bus transmission protocol.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA),
and a Serial Clock line (SCL). The protocol defines any
device that sends data onto the SDA bus as a transmitter,
and the receiving devices as a receiver. The bus is
controlled by Master device which generates the SCL,
controls the bus access and generates the Stop and Start
conditions. The IS24C256 is the Slave device on the bus.
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the data line must remain stable
whenever the clock line is high. Any changes in the
data line while the clock line is high will be interpreted
as a Start or Stop condition.
The state of the data line represents valid data after a Start
condition. The data line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated
with a Stop condition.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when
SCL is High. The IS24C256 monitors the SDA and SCL
lines and will not respond until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with
a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS24C256 contains a reset function in case the 2-
wire bus transmission is accidentally interrupted (eg. a
power loss), or needs to be terminated mid-stream.
The reset is caused when the Master device creates a
Start condition. To do this, it may be necessary for the
Master device to monitor the SDA line while cycling the
SCL up to nine times. (For each clock signal transition
to High, the Master checks for a High level on SDA.)
Standby Mode
Power consumption in reduced in standby mode. The
IS24C256 will enter standby mode: a) At Power-up, and
remain in it until SCL or SDA toggles; b) Following the Stop
signal if no write operation is initiated; or c) Following any
internal write operation
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave
(Fig. 5) address is 8 bits.
The four most significant bits of the address are fixed as
1010 for the IS24C256.
This device has three address bits (A1, A2, and A0),
which allows up to eight IS24C256 devices to share the
2-wire bus. Upon receiving the Slave address, the
device compares the three address bits with the
hardwired A2, A1, and A0 input pins to determine if it is
the appropriate Slave. If the A2, A1, and A0 pins are
not biased to High nor Low, then internal circuitry
defaults the value to Low.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master transmits the Start condition and
Slave address byte (Fig. 5), the appropriate 2-wire
Slave (eg. IS24C256) will respond with ACK on the
SDA line. The Slave will pull down the SDA on the
ninth clock cycle, signaling that it received the eight
bits of data. The selected IS24C256 then prepares for a
Read or Write operation by monitoring the bus.
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends two byte addresses that are to
be written into the address pointer of the IS24C256. After
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memory location. The IS24C256 acknowledges once more
and the Master generates the Stop condition, at which time
the device begins its internal programming cycle. While
this internal cycle is in progress, the device will not respond
to any request from the Master device.
4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
03/11/03

4페이지










IS24C256-3ZI 전자부품, 판매, 대치품
IS24C256
Figure 4. Data Validity Protocol
SCL
SDA
Data Change
Data Stable
Data Stable
Figure 5. Slave Address
BIT 7 6 5 4 3 2 1 0
1 0 1 0 A2 A1 A0 R/W
ISSI®
Figure 6. Byte Write
S
T
A
R
T
SDA
Bus
Activity
M
S
B
Device
Address
W
R
I
T
E
Word Address
Word Address
AA
C* C
KK
LM
S
B
S
B
R/W
* = Don't care bit
A
C
K
Data
S
T
O
P
A
C
K
Figure 7. Page Write
S
T
A
R
T
SDA
Bus
Activity
Device
Address
W
R
I
T
E Word Address (n) Word Address (n)
A AA
C* C
KK
C
K
ML
SS
BB
R/W
* = Don't care bit
Data (n)
A
C
K
Data (n+1)
A
C
K
Data (n+63)
S
T
O
P
A
C
K
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
03/11/03
7

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