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PDF ISL5217 Data sheet ( Hoja de datos )
| Número de pieza | ISL5217 | |
| Descripción | Quad Programmable Up Converter | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
March 2003
ISL5217
FN6004.2
Quad Programmable Up Converter
The ISL5217 Quad Programmable
UpConverter (QPUC) is a QASK/FM
modulator/FDM upconverter designed
for high dynamic range applications such as cellular
basestations. The QPUC combines shaping and interpolation
filters, a complex modulator, and timing and carrier NCOs into a
single package. Each QPUC can create four FDM channels.
Multiple QPUCs can be cascaded digitally to provide for up to 16
FDM channels in multi-channel applications.
The ISL5217 supports both vector and FM modulation. In vector
modulation mode, the QPUC accepts 16-bit I and Q samples to
generate virtually any quadrature AM or PM modulation format.
The QPUC also has two FM modulation modes. In the FM with
pulse shaping mode, the 16-bit frequency samples are pulse
shaped/bandlimited prior to FM modulation. No band limiting filter
follows the FM modulator. This FM mode is useful for GMSK type
modulation formats. In the FM with band limiting filter mode, the
16-bit frequency samples directly drive the FM modulator. The
FM modulator output is filtered to limit the spectral occupancy.
This FM mode is useful for analog FM or FSK modulation
formats.
The QPUC includes an NCO driven interpolation filter, which
allows the input and output sample rate to have an integer
and/or variable relationship. This re-sampling feature
simplifies cascading modulators with sample rates that do not
have harmonic or integer frequency relationships.
The QPUC offers digital output spectral purity that exceeds
100dB at the maximum output sample rate of 104MSPS, for
input sample rates as high as 6.5MSPS.
A 16-bit microprocessor compatible interface is used to load
configuration and baseband data. A programmable FIFO depth
interrupt simplifies the interface to the I and Q input FIFOs.
Block Diagram
Features
• Output Sample Rates Up to 104MSPS with Input Data
Rates Up to 6.5MSPS
• Processing Capable of >140dB SFDR Out of Band
• Vector modulation for supporting IS-136, EDGE, IS95, TD-
SCDMA, CDMA-2000-1X/3X, W-CDMA, and UMTS
• FM Modulation for Supporting AMPS, NMT, and GSM
• Four Completely Independent Channels on Chip, Each With
Programmable 256 Tap Shaping FIR, Half-Band, and High
Order Interpolation Filters
• 16-Bit parallel µProcessor Interface and Four Independent
Serial Data Inputs
• Two 20-bit I/O Buses and Two 20-bit Output Buses Allow
Cascading Multiple Devices
• 32-Bit Programmable Carrier NCO; 48-Bit Programmable
Symbol Timing NCOs
• Dynamic Gain Profiling and Output Routing Control
Applications
• Single or Multiple Channel Digital Software Radio
Transmitters (Wide-Band or Narrow-Band)
• Base Station Transmitter and Smart Antennas
• Operates with HSP50216 in Software Radio Solutions
• Compatible with the HI5960/ISL5961 or HI5828/ISL5929
D/A Converters
Ordering Information
PART
NUMBER
ISL5217KI
ISL5217EVAL1
TEMP
RANGE (oC) PACKAGE
-40 to 85 196 Ld BGA
25 Evaluation Kit
PKG. NO
V196.15x15
SDA
SDB INPUT I/Q SHAPING I/Q I/Q HALF I/Q INTPL I/Q COMPLEX I/Q
SDC
SDD
DATA
FILTER/
FM MOD.
BAND
FILTER
MIXER
SIN COS
CARRIER
NCO
SAMPLE
NCO
CHANNEL 0
CHANNEL 1
P<15:0>
A<6:0>
{CNTRL}
PARALLEL HOST INTERFACE
CHANNEL 2
CHANNEL 3
CONFIGURATION AND CONTROL BUS
I0
Q0 4 CH
I1 SUM
ΣQ1
I2
Q2
ΣI3
Q3 1
Σ2
Σ3
Σ4
DELAY
SUM
CAS IOUT(19:0)
SUM
CAS
SUM QOUT(19:0)
QIN(19:0)
IIN(19:0)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. CommLink™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL5217
Pin Descriptions (all signals are active high unless otherwise stated) (Continued)
NAME
TYPE
DESCRIPTION
TXENA,
TXENB,
TXENC,
TXEND
I Transmit Enable A-D. (TXENX) The processing channel selected for this enable will force a channel flush
(conditioned by control word 0x0c, bit 2), clear the data RAMs, and update the selected configuration registers upon
assertion. No additional requests for serial data will be made when TXENX is deasserted, unless conditioned by
control word 0x0c, bit 3. The polarity of TXENX is programmable. Optionally, TXENX can be internally generated
with a programmable duty cycle. Two different programmable TXENX cycles can be programmed and toggled
between based on programmed cycle length. See control word 0x0c, bit 11 and Table 43 for additional details.
UPDA, UPDB, I Update A-D. (UPDX) The processing channel selected for this input updates the selected configuration registers, if
UPDC, UPDD
the associated update mask bit is set. The polarity of UPDX is programmable.
SYNCO
O Synchronization Output. The processing of multiple ISL5217 devices can be synchronized through software by
connecting the SYNCO of the master ISL5217 device to an UPDX pin of the ISL5217 slaves. The polarity of SYNCO
is programmable.
MODULATED DATA (80)
IOUT(19:0)
O Output Data Bus A (19:0). Output bus A contains the digital modulated QUC output samples from Output
Summer/Formatter 1. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.
QOUT(19:0)
O Output Data Bus B (19:0). The output bus contains the digital modulated QUC output samples from Output
Summer/Formatter 2. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.
IIN(19:0)
I/O I Cascade In (19:0) or OUTPUT BUS C. Dual function I/O bus. The bus is configured for input when the output mode
is cascade in. The bus is configured for output for all other output modes.
I Cascade In. Input bus allows multiple parts to be cascaded by routing the digital modulated signal I CAS OUT,
(Bus A), from one QUC into Output Summer/Formatter 1 of a second QUC. I CAS IN (19:0) is in 2’s complement
format and is sampled on the rising edge of CLK. Bit<19> is the MSB.
Output Data Bus C. The output bus contains the digital modulated QUC output samples from Output
Summer/Formatter 3. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.
QIN(19:0)
I/O Q Cascade in (19:0) or Output Data Bus D. Dual function I/O bus. The bus is configured for input when the output
mode is cascade in. The bus is configured for output for all other output modes.
Q Cascade in. Input bus allows multiple parts to be cascaded by routing the digital modulated signal Q CAS OUT,
(Bus B), from one QUC into Output Summer/Formatter 2 of a second QUC. Q CAS IN (19:0) is in 2’s complement
format and is sampled on the rising edge of CLK. Bit<19> is the MSB.
Output Data Bus D. The output bus contains the digital modulated QUC output samples from Output
Summer/Formatter 4. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.
ISTRB
O I data strobe. (active high). Used in the muxed I/Q mode. When asserted, the output data buses contain valid I data.
JTAG TEST ACCESS PORT
TMS
I JTAG Test Mode Select. Internally pulled up.
TDI I JTAG Test Data In. Internally pulled up.
TCK
I JTAG Test Clock.
TRST
I JTAG Test Reset (Active Low). Internally pulled-up. This pin should be driven by the JTAG logic to obtain a TAP
controller reset, or if JTAG is not utilized, this pin should be tied to ground for normal operation. As recommended
in the 1149.1 standard documentation the TRST test pin should be made active soon after power-up to guarantee
a known state within the TAP logic on the ISL5217. This avoids potential damage due to signal contention at the
circuit’s inputs and outputs.
TDO
O JTAG Test Data Out.
5
5 Page 
ISL5217
Polyphase output 1 = (D1*D[n]) + (D5*D[n-1]) + (D9*D[n-2])
+ (D13*D[n-3])
Polyphase output 2 = (D2*D[n]) + (D6*D[n-1]) + (D10*D[n-2])
+ (D14*D[n-3])
Polyphase output 3 = (D3*D[n]) + (D7*D[n-1]) + (D11*D[n-2])
+ (D15*D[n-3])
Table 4 details the coefficient address allocation for the
previous example. The interpolation phase is on the left and
the data span is across the top. The coefficient RAM address
followed by the coefficient term is listed in the table’s cell.
Table 49 details the coefficient address locations through
255.
TABLE 4. ADDRESS ALLOCATION
DS [n] DS [n-1] DS [n-2] DS [n-3]
IP0 0 CO 16 C4 32 C8 48 C12 •
IP1 1 C1 17 C5 33 C9 49 C13 •
IP2 2 C2 18 C6 34 C10 50 C14 •
IP3 3 C3 19 C7 35 C11 51 C15 •
IP4 4 20 36 52 •
IP5 5 21 37 53 •
IP6 6 22 38 54 •
IP7 7 23 39 55 •
IP8 8 D0 24 D4 40 D8 56 D12 •
IP9 9 D1 25 D5 41 D9 57 D13 •
IP10 10 D2 26 D6 42 D10 58 D14 •
IP11 11 D3 27 D7 43 D11 59 D15 •
IP12 12
28
44
60
•
IP13 13
29
45
61
•
IP14 14
30
46
62
•
IP15 15
31
47
63
•
The loading options are programmable including read back
modes and are discussed in detail in the ‘Microprocessor
Interface’ section. Both 16-bit 2’s complement and 24-bit
floating point format are allowed. The 2’s complement
coefficient format of valid digital values ranges from 0x8001
to 0x7FFF. The value 8000 is not allowed. The 24-bit floating
point (20-bit mantissa with 4-bit exponent) mode allows an
exponent range from 0 to 15. An exponent of 0 indicates
multiplication of the coefficient by 20, and an exponent of 1 is
2-1, down to a value of 15 being 2-15. The default mode is 2’s
complement, with 24-bit floating point mode enabled by
setting control word (0x17, bit 12).
The gain through the filter is:
A = (sum of coefficients) / interpolation rate.
The shaping filter contains saturation logic in the event that
the final output peaks over +/- 1.0. When using quadrature
modulation, saturation/overflow can occur when the input
values for I and Q exceed 0.707 peak. The shaping filter
coefficients may need to be reduced from full scale to
prevent saturation.
Gain Profile
The overall channel gain is controlled by both a gain profile
stage and a gain control stage, which provide identical scaling
for the I and Q upconverted data. The gain profile stage allows
transmit ramp-up and quench fading, to control the sidelobe
profile in burst mode. This is implemented through user control
of the rise and fall transitions utilizing a gain profile memory.
The gain profile memory is a 128 x 12 bit RAM which is loaded
with the desired scaling coefficients via indirect addressing of
memory spaces 0x000-0x07f. The pulse shaping is
implemented by linearly multiplying the programmed coefficient
by the shaping filter outputs at the fS*IP, or coarse phase rate.
The gain profile is enabled by FIR control (0xd, bit 15), with the
RAM address pointer being reset to zero on assertion of the
gain profile enable. Control of the pulse shaping is based on
TXENX, as the TXENX rising edge causes the RAM pointer to
begin stepping through the profile until the RAM pointer
matches the Gain profile length programed into control word
(0x0b, bits 6:0). The falling edge of TXENX reverses the
process and the RAM pointer begins decrementing until it
reaches zero. The gain process is symmetric with respect to the
rising or falling edges of TXENX. The latency through the gain
profile block is set by control word (0x0b, bits 8:7) where bit 8
bypasses all latency alignment circuitry and uses TXENX as
input to the channel. Setting control word (0x0b, bit 7) removes
two edge latencies from the delay path and should be
combined with selection of DS = 3, IP = 4 in order to have
perfect symmetry through the gain profile block. The memory
coefficients may be loaded without taking the channel off-line.
This is implemented by setting the gain profile hold bit in control
word (0x0c, bit 14) which holds the last gain value and provides
access to the memory.
The gain profile coefficients are programmed as unsigned
values:
Bit weight 20.2-1 2-2... 2-11
Maximum 0x800 = 1.0
0x001 = 2-11
Minimum 0x000 = 0.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL5217.PDF ] | |
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