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JLC1562BF 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 JLC1562BF은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 JLC1562BF 자료 제공

부품번호 JLC1562BF 기능
기능 I2C Bus I/O Expander
제조업체 ON Semiconductor
로고 ON Semiconductor 로고


JLC1562BF 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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JLC1562BF 데이터시트, 핀배열, 회로
JLC1562B
I2C Bus I/O Expander
The JLC1562B facilitates easy I2C Bus expandibility. Multiple
devices (up to 8 on the same I2C Bus) are easily added as each device
has its own selectable 3−bit address. The JLC1562B provides an 8−bit
bidirectional input/output port and 6−bit resolution Digital to Analog
Converter. The voltage on pins P0−P4 is compared with a controllable
threshold voltage and the results are readable through the I2C Bus.
I2C Bus interface pins SDA, SCL and A0−A2 are; Serial Data,
Serial Clock and Device Address respectively. External interface pins
are P0−P7 and VDAC; I/O Port and D/A output.
Features
Pb−Free Packages are Available*
Low Power Dissipation
I2C−Bus Format (2−Wire Type; SDA, SCL) Data Transfer
6−bit DAC
Bus Address Selectable (3−bit)
Address Input Pins are Pulled Up to VDD with Internal Resistor
I/O Pins are Open Drain Outputs
5 Comparators at Inputs
Inputs Protected from External Bus Currents in Power Down Mode
A0 1
A1 2
A2 3
P0 4
P1 5
P2 6
P3 7
VSS 8
16 VDD
15 SDA
14 SCL
13 VDAC
12 P7
11 P6
10 P5
9 P4
Figure 1. Pin Assignment
A0−A2
P0−P4
P5−P7
SCL
SDA
VDAC
PIN LIST
Chip Address Input
Comparator Input / Open Drain Output
Comparator Input / Open Drain Output
Serial Clock Input
I2C Data Output
DAC Output
http://onsemi.com
PDIP−16
N SUFFIX
CASE 648
EIAJ−16
F SUFFIX
CASE 966
MARKING
DIAGRAMS
16
JLC1562BN
AWLYYWW
1
16
JLC1562B
ALYW
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
JLC1562BN
PDIP−16
500 / Unit PAK
JLC1562BNG
PDIP−16
(Pb−Free)
500 / Unit PAK
JLC1562BF
JLC1562BFEL
EIAJ−16
(Pb−Free)
EIAJ−16
(Pb−Free)
50 Units / Rail
2000 Units / Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2004
July, 2004 − Rev. 4
1
Publication Order Number:
JLC1562B/D




JLC1562BF pdf, 반도체, 판매, 대치품
DA COMPARATOR CHARACTERISTICS
JLC1562B
Symbol
DNL
eFS
eZC
Parameter
DAC Referential NON−Linearity
DAC Full Scale Error
DAC Zero Scale Error
TIMING CHARACTERISTICS
Symbol
fCL
tBUF
tHD:STA
tLOW
tHIGH
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Parameter
SCL CLOCK Frequency
BUS Free Time (Between “STOP” and “START”)
HOLD Time for “START”
HOLD Time at SCL CLOCK LOW
HOLD Time at SCL CLOCK HI
DATA HOLD Time
DATA SETUP Time
Rise Time (SDA and SCL)
Fall Time (SDA and SCL)
SETUP Time for “STOP”
Guaranteed Limit
Min Typ Max
±1/4 LSB
±1 LSB
±1 LSB
Unit
Guaranteed Limit
Min Max
0 100
4.7 −
4.0 −
4.7 −
4.0 −
0−
250 −
− 1000
− 300
4.0 −
Unit
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
SDA
SCL
tBUF
tLOW
tR
tF
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STO
http://onsemi.com
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JLC1562BF 전자부품, 판매, 대치품
JLC1562B
<<WRITE MODE>>
12 34 5 6 7 8 9 12 34 56 7 8 9 1 2 3 4 5 67 8 9
SCL
WRITE COMMAND
DATA (I)
DATA (II)
SDA
S0 111 x x x 0A
Write_buffer
Latch Pulse
I/O Port
(P0 − P7)
DAC
Latch Pulse
DAC Latch
A AP
DATA (I) valid
DATA (II) valid
<<READ MODE>> (READ LATCH = 0)
12 34 5 6 7 8 9 12 34 56 7 8 9
SCL
READ COMMAND
DATA (I) + (II)
SDA
S0 1 1 1 x x x 1A
PISO
Load Pulse
Comp_out
(C0 − C4)
Comp_out
(C5 − C7)
DATA (I)
DATA (II)
AP
<<READ MODE>> (READ LATCH = 1)
12 34 5 6 7 8 9
SCL
WRITE DATA (II)
SDA
1
DAC Latch
D7 (READ LATCH Bit)
LATCH Reset
AP
Comp._out
Latched Data
PISO
Load Pulse
1234 56789123456789
READ COMMAND
S0 111 x x x 1A
DATA (I)
AP
DATA (I)
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관련 데이터시트

부품번호상세설명 및 기능제조사
JLC1562B

I2C Bus I/O Expander

ON Semiconductor
ON Semiconductor
JLC1562BF

I2C Bus I/O Expander

ON Semiconductor
ON Semiconductor

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