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부품번호 K6E0808C1E-L 기능
기능 32K x 8 Bit High-Speed CMOS Static RAM
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


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K6E0808C1E-L 데이터시트, 핀배열, 회로
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
For Cisco
CMOS SRAM
Document Title
32Kx8 Bit High-Speed CMOS Static RAM(5V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev.No. History
Rev. 0.0 Initial release with Preliminary.
Rev. 1.0 Release to Final Data Sheet.
Rev. 2.0 2.1. Add Low Power Version.
2.2. Add data retention charactoristic.
Draft Data
Aug. 1. 1998
Nov. 2. 1998
Feb. 25. 1999
Remark
Preliminary
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 2.0
Feburary 1999




K6E0808C1E-L pdf, 반도체, 판매, 대치품
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
For Cisco
CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
Value
0V to 3V
3ns
1.5V
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(A)
DOUT
255
+5V
480
30pF*
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
DOUT
255
+5.0V
480
5pF*
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tPU
tPD
K6E0808C1E-10
Min Max
10 -
- 10
- 10
-5
3-
0-
05
05
3-
0-
- 10
* The above parameters are also guaranteed at industrial temperature range.
K6E0808C1E-12
Min Max
12 -
- 12
- 12
-6
3-
0-
06
06
3-
0-
- 12
K6E0808C1E-15
Min Max
15 -
- 15
- 15
-7
3-
0-
07
07
3-
0-
- 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-4-
Revision 2.0
Feburary 1999

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K6E0808C1E-L 전자부품, 판매, 대치품
K6E0808C1E-C/E-L, K6E0808C1E-I/E-P
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
For Cisco
CMOS SRAM
Address
CS
WE
Data in
Data out
tAS(4)
High-Z
tWC
tAW
tCW(3)
tWP1(2)
tWR(5)
tWHZ(6)
tDW tDH
Valid Data
High-Z(8)
tOW (10) (9)
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
Address
CS
tAS(4)
tWC
tAW
tCW(3)
tWP(2)
WE
Data in
Data out
High-Z
High-Z
tLZ tWHZ(6)
tWR(5)
tDW
Valid Data
tDH
High-Z
High-Z(8)
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end
of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
-7-
Revision 2.0
Feburary 1999

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