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K6R1008C1A-C15 데이터시트 PDF




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부품번호 K6R1008C1A-C15 기능
기능 128Kx8 High Speed Static RAM5V Operating/ Revolutionary Pin out. Operated at Commercial and Industrial Temperature Ranges.
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K6R1008C1A-C15 데이터시트, 핀배열, 회로
PRELIMINARY
K6R1008C1A-C, K6R1008C1A-I
CMOS SRAM
Document Title
128Kx8 High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev. No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
Rev. 3.0
Rev. 4.0
History
Initial release with Preliminary.
Release to final Data Sheet.
1.1. Delete Preliminary
Update D.C parameters.
2.1. Update D.C parameters
ITEMS
Previous spec.
(12/15/17/20ns part)
ICC 200/190/180/170mA
ISB 30mA
ISB1 10mA
Updated spec.
(12/15/17/20ns part)
170/165/165/160mA
25mA
8mA
Add Industrial Temperature Range parts and 300mil-SOJ PKG.
3.1. Add 32-Pin 300mil-SOJ Package.
3.2. Add Industrial Temperature Range parts with the same parame-
ters as Commercial Temperature Range parts.
3.2.1. Add K6R1008C1A parts for Industrial Temperature Range.
3.2.2. Add ordering information.
3.2.3. Add the condition for operating at Industrial Temp. Range.
3.3. Add the test condition for VOH1 with VCC=5V±5% at 25°C
3.4. Add timing diagram to define tWP as ″(Timing Wave Form of
Write Cycle(CS=Controlled)
4.1. Delete 17ns Part
Draft Data
Apr. 22th, 1995
Feb. 29th, 1996
Remark
Preliminary
Final
Jul. 16th, 1996
Final
Jun. 2nd, 1997
Final
Feb. 25th, 1998 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 4.0
February 1998




K6R1008C1A-C15 pdf, 반도체, 판매, 대치품
PRELIMINARY
K6R1008C1A-C, K6R1008C1A-I
CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(A)
DOUT
255
+5.0V
480
30pF*
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
DOUT
255
+5.0V
480
5pF*
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tPU
tPD
K6R1008C1A-12
Min Max
12 -
- 12
- 12
-6
3-
0-
06
06
3-
0-
- 12
* The above parameters are also guaranteed at industrial temperature range.
K6R1008C1A-15
Min Max
15 -
- 15
- 15
-7
3-
0-
07
07
3-
0-
- 15
K6R1008C1A-20
Min Max
20 -
- 20
- 20
-9
3-
0-
09
09
3-
0-
- 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-4-
Rev 4.0
February 1998

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K6R1008C1A-C15 전자부품, 판매, 대치품
PRELIMINARY
K6R1008C1A-C, K6R1008C1A-I
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
Address
CS
tAS(4)
tWC
tAW
tCW(3)
tWP(2)
WE
Data in
Data out
High-Z
High-Z
tLZ tWHZ(6)
tWR(5)
tDW
Data Valid
tDH
High-Z
High-Z(8)
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
CS WE
HX
LH
LH
LL
* X means Dont Care.
OE
X*
H
L
X
Mode
Not Select
Output Disable
Read
Write
I/O Pin
High-Z
High-Z
DOUT
DIN
Supply Current
ISB, ISB1
ICC
ICC
ICC
-7-
Rev 4.0
February 1998

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K6R1008C1A-C12

128Kx8 High Speed Static RAM5V Operating/ Revolutionary Pin out. Operated at Commercial and Industrial Temperature Ranges.

Samsung semiconductor
Samsung semiconductor
K6R1008C1A-C15

128Kx8 High Speed Static RAM5V Operating/ Revolutionary Pin out. Operated at Commercial and Industrial Temperature Ranges.

Samsung semiconductor
Samsung semiconductor

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