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부품번호 K7B801825B 기능
기능 256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
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K7B801825B 데이터시트, 핀배열, 회로
K7B403625M
Document Title
128Kx36-Bit Synchronous Burst SRAM
128Kx36 Synchronous SRAM
Revision History
Rev. No. History
Draft Date
0.0 Initial draft
May. 15. 1997
0.1 Modify power down cycle timing & Interleaved read timing,
Insert Note 4 at AC timing characteristics.
Change ISB1 value from 10mA to 30mA.
Change ISB2 value from 10mA to 20mA.
Feb. 11. 1998
0.2 Change Undershoot spec
from -3.0V(pulse width20ns) to -2.0V(pulse widthtCYC/2)
Add Overshoot spec 4.6V((pulse widthtCYC/2)
Change VIH max from 5.5V to VDD+0.5V
April. 14. 1998
0.3 Change ISB2 value from 20mA to 30mA.
May. 13. 1998
Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V.
1.0 Final spec Release
May. 15. 1998
2.0 Add VDDQ Supply voltage( 2.5V )
Dec. 02. 1998
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - December 1998
Rev 2.0




K7B801825B pdf, 반도체, 판매, 대치품
K7B403625M
128Kx36 Synchronous SRAM
FUNCTION DESCRIPTION
The K7B403625M is a synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power PC
based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration
of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both
GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are
sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the
output pins.
Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and
individual byte write operation.
All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high
and BW is low. In K7B403625M, a 128Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and
DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd.
CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded.
ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when ADV is sampled low.
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
00
11
10
Case 3
A1 A0
10
11
00
01
(Interleaved Burst)
Case 4
A1 A0
11
10
01
00
BURST SEQUENCE TABLE
LBO PIN
LOW
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
10
11
00
Note : 1. LBO pin must be tied to high or low, and floating state must not be allowed.
Case 3
A1 A0
10
11
00
01
(Linear Burst)
Case 4
A1 A0
11
00
01
10
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION
ZZ OE I/O STATUS
Sleep Mode
HX
High-Z
Read
LL
LH
DQ
High-Z
Write
L X Din, High-Z
Deselected
LX
High-Z
Notes
1. X means "Don't Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffersmust
be disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current
does not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
- 4 - December 1998
Rev 2.0

4페이지










K7B801825B 전자부품, 판매, 대치품
K7B403625M
128Kx36 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Input Leakage Current(except ZZ) IIL VDD=Max , VIN=VSS to VDD
-2
Output Leakage Current
IOL Output Disabled, VOUT=VSS to VDDQ
-2
Operating Current
Device Selected, IOUT=0mA,
ICC ZZVIL, All Inputs=VIL or VIH
Cycle Time tCYC min
-75 -
-80 -
-90 -
Standby Current
Device deselected, IOUT=0mA,
ISB ZZVIL, f=Max,
All Inputs0.2V or VDD-0.2V
-75 -
-80 -
-90 -
ISB1
Device deselected, IOUT=0mA, ZZ0.2V, f=0,
All Inputs=fixed (VDD-0.2V or 0.2V)
-
ISB2
Device deselected, IOUT=0mA, ZZVDD-0.2V,
f=Max, All InputsVIL or VIH
-
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
VIH
VIL
VIH
IOL = 8.0mA
IOH = -4.0mA
IOL = 1.0mA
IOH = -1.0mA
-
2.4
-
2.0
-0.5*
2.0
-0.3*
1.7
* VIL(Min)=-2.0(Pulse Width tCYC/2)
** VIH(Max)=4.6(Pulse Width tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V
MAX
+2
+2
350
325
300
100
90
80
30
30
0.4
-
0.4
-
0.8
VDD+0.5**
0.7
VDD+0.5**
UNIT
µA
µA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)
PARAMETER
VALUE
Input Pulse Level(for 3.3V I/O)
0 to 3V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
2ns
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
2ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
VDDQ/2
Output Load
See Fig. 1
- 7 - December 1998
Rev 2.0

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