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K7B801825B-QC65 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K7B801825B-QC65은 전자 산업 및 응용 분야에서
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부품번호 K7B801825B-QC65 기능
기능 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


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K7B801825B-QC65 데이터시트, 핀배열, 회로
K7B803625B
K7B801825B
256Kx36 & 512Kx18 Synchronous SRAM
Document Title
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No.
0.0
0.1
0.2
1.0
2.0
2.1
3.0
History
Initial draft
Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
1. Final spec release
2. Change ISB2 form 50mA to 60mA
Change ordering information( remove 225MHz at SPB)
1. Delete 119BGA package
1. Remove x32 organization
2. Remove -85 speed bin
Draft Date
Remark
May. 18 . 2001 Preliminary
Aug. 11. 2001 Preliminary
Aug. 28. 2001 Preliminary
Nov. 16. 2001 Final
April. 01. 2002 Final
April. 04. 2003 Final
Nov. 17. 2003 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - Nov. 2003
Rev 3.0




K7B801825B-QC65 pdf, 반도체, 판매, 대치품
K7B803625B
K7B801825B
PIN CONFIGURATION(TOP VIEW)
256Kx36 & 512Kx18 Synchronous SRAM
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
VDD
N.C.
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7B803625B(256Kx36)
80 DQPb
79 DQb7
78 DQb6
77 VDDQ
76 VSSQ
75 DQb5
74 DQb4
73 DQb3
72 DQb2
71 VSSQ
70 VDDQ
69 DQb1
68 DQb0
67 VSS
66 N.C.
65 VDD
64 ZZ
63 DQa7
62 DQa6
61 VDDQ
60 VSSQ
59 DQa5
58 DQa4
57 DQa3
56 DQa2
55 VSSQ
54 VDDQ
53 DQa1
52 DQa0
51 DQPa
PIN
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
Address Inputs
32,33,34,35,36,37,43
44,45,46,47,48,49,50
81,82,99,100
ADV
Burst Address Advance 83
ADSP
Address Status Processor 84
ADSC
Address Status Controller 85
CLK Clock
89
CS1 Chip Select
98
CS2 Chip Select
97
CS2 Chip Select
92
WEx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
Output Enable
86
GW
Global Write Enable
88
BW
Byte Write Enable
87
ZZ
Power Down Input
64
LBO
Burst Mode Control
31
VDD
VSS
N.C.
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
VDDQ
VSSQ
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
No Connect
14,16,38,39,42,66
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
Output Ground
5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
- 4 - Nov. 2003
Rev 3.0

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K7B801825B-QC65 전자부품, 판매, 대치품
K7B803625B
K7B801825B
256Kx36 & 512Kx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 CS2 CS2 ADSP ADSC ADV WRITE CLK ADDRESS ACCESSED
HXXXLX X
N/A
L LXLXX X
N/A
LXHLXX X
N/A
L LXXLX X
N/A
LXHXLX X
N/A
LHL LXX X
External Address
LHLHLX L
External Address
LHLHLX H
External Address
XXXHHL H
Next Address
HXXXHL H
Next Address
XXXHHL L
Next Address
HXXXHL L
Next Address
XXXHHH H
Current Address
HXXXHH H
Current Address
XXXHHH L
Current Address
HXXXHH L
Current Address
Notes : 1. X means "Dont Care". 2. The rising edge of clock is symbolized by .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
OPERATION
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
WRITE TRUTH TABLE( x36)
GW
BW
WEa
WEb
WEc
WEd
HHXXXX
H L HHHH
HL LHHH
H L H L HH
HLHHL L
HL L L L L
LXXXXX
Notes : 1. X means "Dont Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
OPERATION
READ
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
WRITE TRUTH TABLE(x18)
GW
BW
WEa
WEb
HHXX
H L HH
HL LH
HLHL
HL L L
OPERATION
READ
READ
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
LXXX
WRITE ALL BYTEs
Notes : 1. X means "Dont Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
- 7 - Nov. 2003
Rev 3.0

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K7B801825B-QC65

256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM

Samsung semiconductor
Samsung semiconductor

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