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K7D801871B-HC30 데이터시트 PDF




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부품번호 K7D801871B-HC30 기능
기능 256Kx36 & 512Kx18 SRAM
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K7D801871B-HC30 데이터시트, 핀배열, 회로
K7D803671B
K7D801871B
256Kx36 & 512Kx18 SRAM
Document Title
8M DDR SYNCHRONOUS SRAM
Revision History
Rev No.
History
Rev. 0.0 -Initial document.
Rev. 0.1 -ZQ tolerance changed from 10% to 15%
Rev. 0.2
-Stop Clock Standby Current condition changed from
VIN=VDD-0.2V or 0.2V fixed to VIN=VIH or VIH
Rev. 0.3
-VDDQ Max. changed to 2.0V
SA0, SA1 defined for Boundary Scan Order
Rev. 0.5 -Deleted -HC16 part(Part Number, Idd, AC Characterisctics)
Rev. 0.6
- Absolute Maximum ratings VDDQ changed from 3.13V to 2.825V
Rev. 0.7
- LBO input level changed from High/Low to VDDQ/VSS
- Stop Clock Standby Current condition changed
from K=Low, K=High to K=Low, K=Low
- tCHQV/tCLQV changed from 0.1ns to 0.2ns for -33 part
from 0.1ns to 0.2ns for -30 part
from 0.1ns to 0.25ns for -25part
- tCHQX/tCLQX changed from -0.3ns to -0.2ns for -33 part
from -0.3ns to -0.2ns for -30 part
from -0.4ns to -0.25ns for -25part
- tCHQZ/tCLQZ changed from 0.1ns to 0.2ns for -33 part
from 0.1ns to 0.2ns for -30 part
from 0.1ns to 0.25ns for -25part
- tKXCH changed from 1.8ns to 1.7ns for -33 part
- tKXCL changed from 1.8ns to 1.7ns for -33 part
Rev. 1.0
- Clarification on the features and the timing waveforms regarding the
burst controllability.
- Recommended DC operating conditions for Clock added.
- AC test conditions for VDDQ=1.8V and Single ended clock added.
(AC Test Conditions 2)
- Package thermal characteristics added.
Rev. 2.0 - Add-HC35 part(Part Number, Idd, AC Characteristics)
Rev. 3.0
- Absolute Maximum Rating VDDQ changed from 2.825V to 2.4V
- VCM-CLK Min changed from 0.6V to 0.68V
Rev. 4.0 - Add-HC37 part(Part Number, Idd, AC Characteristics)
DraftData
July. 2000
Aug. 2000
Oct. 2000
Nov. 2000
Jan. 2001
Feb. 2001
Mar. 2001
Remark
Advance
Advance
Advance
Advance
Prelimary
Prelimary
Prelimary
May. 2001
Final
Sep. 2001
Jan. 2002
Jan. 2002
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-1-
January. 2002
Rev 4.0




K7D801871B-HC30 pdf, 반도체, 판매, 대치품
K7D803671B
K7D801871B
256Kx36 & 512Kx18 SRAM
FUNCTION DESCRIPTION
The K7D803671B and K7D801871B are 9,437,184 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
262,144 words by 36 bits for K7D803671B and 524,288 words by 18 bits for K7D801871B, fabricated using Samsung's advanced
CMOS technology.
Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At
the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after
write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and
falling edge of K clock for a double data rate (DDR) write operations.
Data outputs are updated from output registers off the rising edges of K clock for SDR read operations, and off the rising and falling
edges of K clock for DDR read operations. Free running echo clocks are supported which are representive of data output access
time for all SDR and DDR operations.
The chip is operated with a single +2.5V power supply and is compatible with Extended HSTL input and output. The package is
9x17(153) Ball Grid Array balls on a 1.27mm pitch.
Read Operation(Single and Double)
During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is
read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of
K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal
array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by
burst order off the second rising and falling edge of K clock.
Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.
To avoid data contention,at least one NOP operations are required between the last read and the first write operation.
Write Operation(Late Write)
During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered
at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of
K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are
stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM
array.
Echo clock operation
Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation
only when K clock is in the stop mode.
Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture
data outputs outputs.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array.
Programmable Impedance Output Driver
The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and
are equal to RQ/5. For example, 250resistor will give an output impedance of 50. Output driver impedance tolerance is 15% by
test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates
occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In
all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior
in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is
selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 contin-
uous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are
no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs
1024 non-read cycles.
-4-
January. 2002
Rev 4.0

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K7D801871B-HC30 전자부품, 판매, 대치품
K7D803671B
K7D801871B
256Kx36 & 512Kx18 SRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Core Supply Voltage Relative to VSS
VDD
-0.5 to 3.13
V
Output Supply Voltage Relative to VSS
VDDQ
-0.5 to 2.4
V
Voltage on any pin Relative to VSS
VIN
-0.5 to VDDQ+0.5 (2.4V MAX)
V
Output Short-Circuit Current(per I/O)
Storage Temperature
IOUT
TSTR
25
-55 to 125
mA
°C
NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level Voltage
Input Low Level Voltage
Input Reference Voltage
Clock Input Signal Voltage
Clock Input Differential Voltage
Clock Input Common Mode Voltage
Symbol
VDD
VDDQ
VIH
VIL
VREF
VIN-CLK
VDIF-CLK
VCM-CLK
Min
2.37
1.4
VREF+0.1
-0.3
0.68
-0.3
0.1
0.68
Typ
2.5
1.5
-
-
0.75
-
-
0.75
Max
2.63
2.0
VDDQ+0.3
VREF-0.1
1.0
VDDQ+0.3
VDDQ+0.6
0.9
Unit
V
V
V
V
V
V
V
V
Note
1, 2
1, 3
1, 4
1, 5
1, 6
NOTE : 1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=2.6V (2.1V for DQs) (pulse width 20% of cycle time).
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.0V (-0.5V for DQs) (pulse width 20% of cycle time).
4. VIN-CLK specifies the maximum allowable DC level for the differential clock. i.e VIL-CLK and VIH-CLK.
5. VDIF-CLK specifies the minimum Clock differential voltage required for switching. i.e DC voltage difference between VIL-CLK and VIH-CLK.
6. VCM-CLK specifies the Clock crossing point for the differential clock or the allowable common clock level for a single ended clock.
-7-
January. 2002
Rev 4.0

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부품번호상세설명 및 기능제조사
K7D801871B-HC30

256Kx36 & 512Kx18 SRAM

Samsung semiconductor
Samsung semiconductor
K7D801871B-HC33

256Kx36 & 512Kx18 SRAM

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