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K7P401822B-HC25 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K7P401822B-HC25은 전자 산업 및 응용 분야에서
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부품번호 K7P401822B-HC25 기능
기능 128Kx36 & 256Kx18 Synchronous Pipelined SRAM
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K7P401822B-HC25 데이터시트, 핀배열, 회로
K7P403622M
K7P401822M
128Kx36 & 256Kx18 SRAM
Document Title
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
Revision History
Rev. No. History
Rev. 0.0
- Preliminary specification release
Rev. 0.1
- Change specification format.
No change was made in parameters.
Rev. 0.2
Rev. 1.0
- Updated IDD, ISB and Input High Level.
Updated tKHKL, tKLKH, tKHQX, tKHQX1 and AC Test Conditions.
For JTAG, updated Vendor Definition and added tSVCH/tCHSX.
- Final specification release
Draft Date Remark
Preliminary
April, 1997
Preliminary
Jan. 1998
Preliminary
Dec. 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-1-
Dec. 1998
Rev 1.0




K7P401822B-HC25 pdf, 반도체, 판매, 대치품
K7P403622M
K7P401822M
128Kx36 & 256Kx18 SRAM
FUNCTION DESCRIPTION
The K7P403622M and K7P401822M are 4,718,592 bit Synchronous Pipeline Mode SRAM. It is organized as 131,072words of 36
bits(or 262, 144 words of 18 bits)and is implemented in SAMSUNG’s advanced CMOS technology.
Single differential PECL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the
rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are
updated from output registers edge of the next rising edge of K clock. An internal write data buffer allows write data to follow one
cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
Read Operation
During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second-
edge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this
cycle, signaling that the SRAM should drive out the data.
During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-
ple SRAM cycles to perform a single read operation.
Write(Store) Operation
All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock,
one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the
Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input.
Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write
cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of
read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the
same as the SW signal.
Bypass Read Operation
Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to
be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address
is the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored
write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the
SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have
new byte data from the write data buffer and the other bytes from the SRAM array.
Low Power Dissipation Mode
During normal operation, asynchronous signal ZZ must be pulled low. Low Power Mode is enabled by switching ZZ high. When the
SRAM is in Power Down Mode, the outputs will go to a Hi-Z state and the SRAM will draw standby current. SRAM data will be pre-
served and a recovery time(tZZR) is required before the SRAM resumes to normal operation.
TRUTH TABLE
K ZZ G SS SW SWa SWb SWc SWd DQa DQb DQc DQd
Operation
X H X X X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Power Down Mode. No Operation
X L H X X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled.
L L H X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled. No Operation
L L L H X X X X DOUT DOUT DOUT DOUT Read Cycle
L X L L H H H H Hi-Z Hi-Z Hi-Z Hi-Z No Bytes Written
L X L L L H H H DIN Hi-Z Hi-Z Hi-Z Write first byte
L X L L H L H H Hi-Z DIN Hi-Z Hi-Z Write second byte
L X L L H H L H Hi-Z Hi-Z DIN Hi-Z Write third byte
L X L L H H H L Hi-Z Hi-Z Hi-Z DIN Write fourth byte
L X L L L L L L DIN DIN DIN DIN Write all byte
-4-
Dec. 1998
Rev 1.0

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K7P401822B-HC25 전자부품, 판매, 대치품
K7P403622M
K7P401822M
128Kx36 & 256Kx18 SRAM
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (SS Controlled, G=Low)
K
SAn
SS
SW
SWx
DQn
12345678
tKHKH
tAVKH
tKHAX
tKHKL tKLKH
A1 A2
A3 A4 A5 A4 A6 A7
tSVKH
tKHSX
tWVKH
tKHWX
tWVKH
tKHWX
tWVKH
tKHWX
tKHQV
Q1
tKHQZ tDVKH tKHDX
Q2 D3
tKHDX
D4
tKHQX1
tKHQX
Q5
Q4
NOTE
1. D3 is the input data written in memory location A3.
2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last
write cycle address.
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (G Controlled, SS=Low)
K
SAn
12
tKHKH
A1 A2
345678
A3 A4 A5 A4 A6 A7
G
SW
SWx
DQn
tGHQZ
Q1 Q2
D3 D4
tGLQV
tGLQX
Q5
Q4
NOTE
1. D3 is the input data written in memory location A3.
2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last
write cycle address.
-7-
Dec. 1998
Rev 1.0

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