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K7R161884B-FC30 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K7R161884B-FC30은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 K7R161884B-FC30 자료 제공

부품번호 K7R161884B-FC30 기능
기능 512Kx36 & 1Mx18 QDR II b4 SRAM
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


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K7R161884B-FC30 데이터시트, 핀배열, 회로
K7R163684B
K7R161884B
512Kx36 & 1Mx18 QDRTM II b4 SRAM
Document Title
512Kx36-bit,1Mx18-bit QDRTM II b4 SRAM
Revision History
Rev. No.
History
0.0 1. Initial document.
0.1 1. Change the Boundary scan exit order.
2. Correct the Overshoot and Undershoot timing diagram.
0.2 1. Change JTAG Block diagram
0.3 1. Add the speed bin (-25)
0.4 1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
0.5 1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.
0.6 1. Add the power up/down sequencing comment.
2. Update the DC current parameter (Icc and Isb).
3. Change the Max. speed bin from -33 to -30.
0.7 1. Change the ISB1.
Speed Bin
-30
-25
-20
-16
From
200
180
160
140
To
230
210
190
170
1.0 1. Final spec release
2.0 1. Delete the x8 Org.
2. Delete the 300MHz speed bin
3.0 1. Add the 300MHz speed bin
3.1 1. Change the stand-by current(ISB1)
before after
Isb1 -30 : 230
260
-25 : 210
240
-20 : 190
220
-16 : 170
200
Draft Date
Oct. 17. 2002
Dec. 16, 2002
Remark
Advance
Preliminary
Dec. 26, 2002
Jan. 27, 2003
Mar. 20, 2003
Preliminary
Preliminary
Preliminary
April. 4, 2003
Preliminary
June. 20, 2003
Preliminary
Oct. 20. 2003
Preliminary
Oct. 31, 2003
Nov. 28, 2003
Final
Final
June. 18, 2004
July. 28, 2004
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - July. 2004
Rev 3.1




K7R161884B-FC30 pdf, 반도체, 판매, 대치품
K7R163684B
K7R161884B
512Kx36 & 1Mx18 QDRTM II b4 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7R161884B(1Mx18)
1 2 3 4 5 6 7 8 9 10 11
A CQ VSS/SA* NC W BW1 K NC R SA VSS/SA* CQ
B NC Q9 D9 SA NC
K
BW0
SA
NC
NC
Q8
C NC NC D10 VSS SA NC SA VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC
NC
Q11
VDDQ
VSS
VSS
VSS VDDQ NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS VDDQ NC
NC
Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N
NC
D17
Q16
VSS
SA
SA
SA VSS NC
NC
D1
P NC
NC Q17 SA
SA
C
SA SA NC D0 Q0
R TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 72Mb and 2A for 144Mb.
2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-17
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D
3F,2G,3J,3L,3M,2N
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
NOTE
1
Q0-17
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E
2F,3G,3K,2L,3N,3P
Data Outputs
W
R
BW0, BW1
VREF
ZQ
VDD
VDDQ
VSS
TMS
TDI
TCK
TDO
NC
4A Write Control Pin,active when low
8A Read Control Pin,active when low
7B, 5A
Block Write Control Pin,active when low
2H,10H
Input Reference Voltage
11H Output Driver Impedance Control Input
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
10R JTAG Test Mode Select
11R JTAG Test Data Input
2R JTAG Test Clock
1R JTAG Test Data Output
3A,7A,1B,5B,9B,10B,1C,2C,6C,9C,1D,9D,10D,1E,2E,9E,1F
9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M
2M,9M,1N,9N,10N,1P,2P,9P
No Connect
2
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
- 4 - July. 2004
Rev 3.1

4페이지










K7R161884B-FC30 전자부품, 판매, 대치품
K7R163684B
K7R161884B
512Kx36 & 1Mx18 QDRTM II b4 SRAM
STATE DIAGRAM
POWER-UP
READ NOP
READ
WRITE
WRITE NOP
READ
READ
D count=2
LOAD NEW
READ ADDRESS
D count=0
ALWAYS
READ
D count=2
DDR READ
D count=D count+1
READ
D count=1
ALWAYS
INCREMENT
READ ADDRESS
WRITE
LOAD NEW
WRITE ADDRESS
D count=0
WRITE
D count=2
ALWAYS
WRITE
D count=2
DDR WRITE
D count=D count+1
ALWAYS
WRITE
D count=1
INCREMENT
WRITE ADDRESS
Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case.
3. Read and write state machine can be active simulateneously.
4. State machine control timing sequence is controlled by K.
- 7 - July. 2004
Rev 3.1

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부품번호상세설명 및 기능제조사
K7R161884B-FC30

512Kx36 & 1Mx18 QDR II b4 SRAM

Samsung semiconductor
Samsung semiconductor

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