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부품번호 K9F1608W0A-TCB0 기능
기능 2M x 8 Bit NAND Flash Memory
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K9F1608W0A-TCB0 데이터시트, 핀배열, 회로
K9F1608W0A-TCB0, K9F1608W0A-TIB0
Document Title
2M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 Initial issue.
1.0 Data Sheet 1998.
1.1 Data Sheet 1999.
1) Added CE dont’ care mode during the data-loading and reading
1.2 1) Revised real-time map-out algorithm(refer to technical notes)
1.3 Changed device name
- KM29W16000AT -> K9F1608W0A-TCB0
- KM29W16000AIT -> K9F1608W0A-TIB0
FLASH MEMORY
Draft Date
April 10th 1998
July 14th 1998
April 10th 1999
Remark
Preliminary
Final
Final
July 23th 1999
Sep.15th 1999
Final
Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1




K9F1608W0A-TCB0 pdf, 반도체, 판매, 대치품
K9F1608W0A-TCB0, K9F1608W0A-TIB0
FLASH MEMORY
PRODUCT INTRODUCTION
The K9F1608W0A is a 16.5Mbit(17,301,504 bit) memory organized as 8192 rows by 264 columns. Spare eight columns are located
from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pages
formed by one NAND structures, totaling 2,112 NAND structures of 16 cells. The array organization is shown in Figure 2. The pro-
gram and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array
consists of 512 separately or grouped erasable 4K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9F1608W0A.
The K9F1608W0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O`s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 2M byte physical space requires 21 addresses, thereby requiring three cycles for byte-level addressing : col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F1608W0A.
Table 1. COMMAND SETS
Function
1st. Cycle
Sequential Data Input
80h
Read 1
00h
Read 2
50h
Read ID
90h
Reset
FFh
Page Program
10h
Block Erase
60h
Read Status
70h
2nd. Cycle
-
-
-
-
-
-
D0h
-
Acceptable Command during Busy
O
O
4

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K9F1608W0A-TCB0 전자부품, 판매, 대치품
K9F1608W0A-TCB0, K9F1608W0A-TIB0
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
NVB
Min
502
Typ.
508
Max Unit
512 Blocks
NOTE :
1. The K9F1608W0A may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these
invalid blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are
guaranteed though its initial number could be reduced. (Refer to the attached technical notes)
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
AC TEST CONDITION
(K9F1608W0A-TCB0:TA=0 to 70°C, K9F1608W0A-TIB0:TA=-40 to 85°C, VCC=2.7V ~ 5.5V unless otherwise noted)
Parameter
Vcc=2.7V ~ 3.6V
Value
Vcc=3.6V ~ 5.5V
Input Pulse Levels
0.4V to 2.4V
0.4V to 3.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
0.8V and 2.0V
Output Load
1 TTL GATE and
CL=50pF(3.0V+/-10%),100pF(3.0V~3.6V)
1 TTL GATE and CL = 100pF
CAPACITANCE(TA=25°C, Vcc=5.0V f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
CI/O
CIN
Test Condition
VIL=0V
VIN=0V
NOTE : Capacitance is periodically sampled and not 100% tested.
Min
-
-
Max
10
10
Unit
pF
pF
MODE SELECTION
CLE
ALE
CE
WE
RE
HL L
H
LHL
H
HL L
H
LHL
H
LLL
H
L L LH
L L LHH
XXXXX
XXXXX
X X(1) X X X
XXHXX
NOTE : 1. X can be VIL or VIH
2. WP should be biased to CMOS high or CMOS low for standby.
WP
X
X
H
H
H
X
X
H
H
L
0V/VCC(2)
Mode
Read Mode
Command Input
Address Input(3clock)
Write Mode
Command Input
Address Input(3clock)
Data Input
Sequential Read & Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
tPROG
-
0.25 1.5
ms
Number of Partial Program Cycles in the Same Page
Nop -
- 10 cycles
Block Erase Time
tBERS
-
2 10 ms
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K9F1608W0A-TCB0

2M x 8 Bit NAND Flash Memory

Samsung semiconductor
Samsung semiconductor

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