Datasheet.kr   

K9F1G08Q0M-YCB0 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K9F1G08Q0M-YCB0은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 K9F1G08Q0M-YCB0 자료 제공

부품번호 K9F1G08Q0M-YCB0 기능
기능 1Gb Gb 1.8V NAND Flash Errata
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


K9F1G08Q0M-YCB0 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 38 페이지수

미리보기를 사용할 수 없습니다

K9F1G08Q0M-YCB0 데이터시트, 핀배열, 회로
ELECTRONICS
March. 2003
San 16 Banwol-Ri
Taean-Eup Hwasung- City
Kyungki Do, Korea
Tel.) 82 - 31 - 208 - 6463
Fax.) 82 - 31 -208 - 6799
1Gb 1.8V NAND Flash Errata
Description : Some of AC characteristics are not meeting the specification.
> AC characteristics : Refer to Table
Affected Products : K9F1G08Q0M-YCB0/YIB0, K9F1G16Q0M-YCB0/YIB0
K9K2G08Q0M-YCB0/YIB0, K9K2G16Q0M-YCB0/YIB0
Improvement schedule : The components targeted to meet the specification
is scheduled to be available by workweek 25 along
with the final specification values.
Workaround : Relax the relevant timing parameters according to the table.
Table
Parameters
tWC
Specification
45
Relaxed Condition 80
tWH
15
20
tWP
25
60
UNIT : ns
tRC tREH tRP tREA tCEA
50 15 25 30 45
80 20 60 60 75
Sincerely,
Product Planning & Application Eng.
Memory Division
Samsung Electronics Co.
1




K9F1G08Q0M-YCB0 pdf, 반도체, 판매, 대치품
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
FLASH MEMORY
128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9F1G08Q0M-Y,P
K9F1G16Q0M-Y,P
K9F1G08U0M-Y,P
K9F1G16U0M-Y,P
K9F1G08U0M-V,F
Vcc Range
1.70 ~ 1.95V
2.7 ~ 3.6V
Organization
X8
X16
X8
X16
X8
PKG Type
TSOP1
WSOP1
FEATURES
Voltage Supply
-1.8V device(K9F1GXXQ0M): 1.70V~1.95V
-3.3V device(K9F1GXXU0M): 2.7 V ~3.6 V
Organization
- Memory Cell Array
-X8 device(K9F1G08X0M) : (128M + 4,096K)bit x 8bit
-X16 device(K9F1G16X0M) : (64M + 2,048K)bit x 16bit
- Data Register
-X8 device(K9F1G08X0M): (2K + 64)bit x8bit
-X16 device(K9F1G16X0M): (1K + 32)bit x16bit
- Cache Register
-X8 device(K9F1G08X0M): (2K + 64)bit x8bit
-X16 device(K9F1G16X0M): (1K + 32)bit x16bit
Automatic Program and Erase
- Page Program
-X8 device(K9F1G08X0M): (2K + 64)Byte
-X16 device(K9F1G16X0M): (1K + 32)Word
- Block Erase
-X8 device(K9F1G08X0M): (128K + 4K)Byte
-X16 device(K9F1G16X0M): (64K + 2K)Word
Page Read Operation
- Page Size
- X8 device(K9F1G08X0M): 2K-Byte
- X16 device(K9F1G16X0M) : 1K-Word
- Random Read : 25µs(Max.)
- Serial Access : 50ns(Min.)
Fast Write Cycle Time
- Program time : 300µs(Typ.)
- Block Erase Time : 2ms(Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
Command Register Operation
Cache Program Operation for High Performance Program
Power-On Auto-Read Operation
Intelligent Copy-Back Operation
Unique ID for Copyright Protection
Package :
- K9F1GXXX0M-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F1G08U0M-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)
- K9F1GXXX0M-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
- K9F1G08U0M-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F1G08U0M-V,F(WSOPI ) is the same device as
K9F1G08U0M-Y,P(TSOP1) except package type.
GENERAL DESCRIPTION
Offered in 128Mx8bit or 64Mx16bit, the K9F1GXXX0M is 1G bit with spare 32M bit capacity. Its NAND cell provides the most cost-
effective solution for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112-
byte(X8 device) or 1056-word(X16 device) page and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device)
or 64K-word(X16 device) block. Data in the data page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for
address and data input/output as well as command input. The on-chip write controller automates all program and erase functions
including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take
advantage of the K9F1GXXX0Ms extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with
real time mapping-out algorithm. The K9F1GXXX0M is an optimum solution for large nonvolatile storage applications such as solid
state file storage and other portable applications requiring non-volatility.
SAMSUNG
3

4페이지










K9F1G08Q0M-YCB0 전자부품, 판매, 대치품
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
(K9F1G08X0M)
I/O0 ~ I/O15
(K9F1G16X0M)
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
COMMAND LATCH ENABLE
CLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
CE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode.
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
WP The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
R/B
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
PRE
POWER-ON READ ENABLE
The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when
PRE pin is tied to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss GROUND
N.C
NO CONNECTION
Lead is not internally connected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
SAMSUNG
6

7페이지


구       성 총 38 페이지수
다운로드[ K9F1G08Q0M-YCB0.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
K9F1G08Q0M-YCB0

1Gb Gb 1.8V NAND Flash Errata

Samsung semiconductor
Samsung semiconductor

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵