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K9F2808Q0B-DCB0 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K9F2808Q0B-DCB0은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 K9F2808Q0B-DCB0 자료 제공

부품번호 K9F2808Q0B-DCB0 기능
기능 16M x 8 Bit NAND Flash Memory
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


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K9F2808Q0B-DCB0 데이터시트, 핀배열, 회로
K9F2808Q0B-DCB0,DIB0 K9F2808U0B-YCB0,YIB0
K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0
Document Title
16M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No. History
0.0 Initial issue.
Draft Date
May 28’th 2001
0.1 K9F2808U0B(3.3V device)’s qualification is finished
Jun. 30th 2001
0.2 K9F2808Q0B (1.8V device)
- Changed typical read operation current (Icc1) from 8mA to 5mA
Jul. 30th 2001
- Changed typical program operation current (Icc2) from 8mA to 5mA
- Changed typical erase operation current (Icc3) from 8mA to 5mA
- Changed typical program time(tPROG) from 200us to 300us
- Changed ALE to RE Delay (ID read, tAR1) from 100ns to 20ns
- Changed CLE hold time(tCLH) from 10ns to 15ns
- Changed CE hold time(tCH) from 10ns to 15ns
- Changed ALE hold time(tALH) from 10ns to 15ns
- Changed Data hold time(tDH) from 10ns to 15ns
- Changed CE Access time(tCEA) from 45ns to 60ns
- Changed Read cycle time(tRC) from 50ns to 70ns
- Changed Write Cycle time(tWC) from 50ns to 70ns
- Changed RE Access time(tREA) from 35ns to 40ns
- Changed RE High Hold time(tREH) from 15ns to 20ns
- Changed WE High Hold time(tWH) from 15ns to 20ns
0.3 1. Device Code is changed
- TBGA package information : ’B’ --> ’D’
ex) K9F2808Q0B-BCB0 ,BIB0 --> K9F2808Q0B-DCB0,DIB0
K9F2808U0B-BCB0 ,BIB0 --> K9F2808Q0B-DCB0,DIB0
2. VIH ,VIL of K9F2808Q0B(1.8 device) is changed
Aug. 23th 2001
(before revision)
Input High Voltage
I/O pins
VccQ-0.4
VIH
Except I/O pins VCC-0.4
-
VccQ
VCC
Input Low Voltage,
All inputs
V IL
-
0 - 0.4
(after revision)
Input High Voltage
I/O pins
VccQ-0.4
VIH
Except I/O pins VCC-0.4
-
Input Low Voltage,
All inputs
V IL
-
-0.3 -
VccQ
+0.3
VCC
+0.3
0.4
Remark
Advance
K9F2808Q0B
: Preliminary
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1




K9F2808Q0B-DCB0 pdf, 반도체, 판매, 대치품
K9F2808Q0B-DCB0,DIB0 K9F2808U0B-YCB0,YIB0
K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0
PIN CONFIGURATION (TSOP1)
K9F2808U0B-YCB0/YIB0
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FLASH MEMORY
48 N.C
47 N.C
46 N.C
45 N.C
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 N.C
39 N.C
38 N.C
37 Vcc
36 Vss
35 N.C
34 N.C
33 N.C
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 N.C
27 N.C
26 N.C
25 N.C
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
2 0 . 0 0± 0 . 2 0
0.787± 0.008
#1 #48
#24
0~8¡Æ
0.45~0.75
0.018~0.030
18.40± 0.10
0.724± 0.004
#25
1 . 0 0± 0 . 0 5
0.039 ±0.002
1.20
0.047
MAX
0.05
0.002
MIN
(
0.50
0.020
)
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K9F2808Q0B-DCB0 전자부품, 판매, 대치품
K9F2808Q0B-DCB0,DIB0 K9F2808U0B-YCB0,YIB0
K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
CE
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’Page read’ section of Device operation.
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE The W E input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
WP The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
R/B
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
VCCQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc POWER
VCC is the power supply for device.
Vss GROUND
NO CONNECTION
N.C Lead is not internally connected.
GND
GND INPUT FOR ENABLING SPARE AREA
To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state.
DNU
DO NOT USE
Leave it disconnected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
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부품번호상세설명 및 기능제조사
K9F2808Q0B-DCB0

16M x 8 Bit NAND Flash Memory

Samsung semiconductor
Samsung semiconductor

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