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부품번호 K9F2808U0M-YCB0 기능
기능 16M x 8 Bit NAND Flash Memory
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K9F2808U0M-YCB0 데이터시트, 핀배열, 회로
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K9F2808U0M-YCB0, K9F2808U0M-YIB0
Document Title
16M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 Initial issue.
1.0 1. Changed tPROG Parameter : 1ms(Max.) 500µs(Max.)
2. Changed tBERS Parameter : 4ms(Max.) 3ms(Max.)
3. Changed Input and Output Timing Level 0.8V and 2.0V 1.5V
1.1 1. Changed tR Parameter : 7µs(Max.) 10µs(Max.)
2. Changed Nop : 10 cycles(Max.) Main Array 2 cycles(Max.)
Spare Array 3 cycles(Max.)
3. Added CE don’t care mode during the data-loading and reading
1.2 1. Revised real-time map-out algorithm(refer to technical notes)
1.3 1. Changed device name
- KM29U128T -> K9F2808U0M-YCB0
- KM29U128IT -> K9F2808U0M-YIB0
1.4 1. Changed SE pin description
- SE is recommended to coupled to GND or Vcc and should not be
toggled during reading or programming.
FLASH MEMORY
Draft Date
April 10th 1998
July 14th 1998
Remark
Preliminary
Final
April 10th 1999
Final
June 30th 1999
Sep. 15th 1999
Final
Final
July 17th 2000
Final
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
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K9F2808U0M-YCB0 pdf, 반도체, 판매, 대치품
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K9F2808U0M-YCB0, K9F2808U0M-YIB0
FLASH MEMORY
PRODUCT INTRODUCTION
The K9F2808U0M is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare sixteen columns
are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data
transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16
cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32
pages formed by one NAND structures, totaling 8448 NAND structures of 16 cells. The array organization is shown in Figure 2. The
program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 1024 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9F2808U0M.
The K9F2808U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/Os by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 16M byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device
operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the
K9F2808U0M.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read 1
00h/01h(1)
-
Read 2
50h(2)
-
Read ID
90h -
Reset
FFh -
O
Page Program
80h 10h
Block Erase
60h D0h
Read Status
70h -
O
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. The 50h command is valid only when the SE(pin 6) is low level.
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K9F2808U0M-YCB0, K9F2808U0M-YIB0
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
NVB
Min
1004
Typ.
-
Max
1024
Unit
Blocks
NOTE :
1. The K9F2808U0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try
to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
AC TEST CONDITION
(K9F2808U0M-YCB0:TA=0 to 70°C, K9F2808U0M-YIB0:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise noted)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load (3.0V +/-10%)
1 TTL GATE and CL=50pF
Output Load (3.3V +/-10%)
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
CI/O
CIN
Test Condition
VIL=0V
VIN=0V
NOTE : Capacitance is periodically sampled and not 100% tested.
Min
-
-
Max
10
10
Unit
pF
pF
MODE SELECTION
CLE
ALE
CE
WE
RE
SE
WP
Mode
HL L
LHL
HXX
Command Input
Read Mode
HXX
Address Input(3clock)
HL L
LHL
HXH
Command Input
Write Mode
HXH
Address Input(3clock)
LLL
H L/H(3) H Data Input
L L LH
L/H(3)
X Sequential Read & Data Output
L L L H H L/H(3) X During Read(Busy)
X X X X X L/H(3) H During Program(Busy)
X X X X X X H During Erase(Busy)
X X(1) X X X X L Write Protect
X X H X X 0V/VCC(2) 0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
3. When SE is high, spare area is deselected.
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Program Time
tPROG
-
200 500
Number of Partial Program Cycles
in the Same Page
Main Array
Spare Array
Nop
-
-
-
-
2
3
Block Erase Time
tBERS
-
2
3
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Unit
µs
cycles
cycles
ms
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K9F2808U0M-YCB0

16M x 8 Bit NAND Flash Memory

Samsung semiconductor
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