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K9F5608Q0C-H 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K9F5608Q0C-H은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 K9F5608Q0C-H 자료 제공

부품번호 K9F5608Q0C-H 기능
기능 32M x 8 Bit / 16M x 16 Bit NAND Flash Memory
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


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K9F5608Q0C-H 데이터시트, 핀배열, 회로
ELECTRONICS
March. 2003
San 16 Banwol-Ri
Taean-Eup Hwasung- City
Kyungki Do, Korea
Tel.) 82 - 31 - 208 - 6463
Fax.) 82 - 31 -208 - 6799
512Mb/256Mb 1.8V NAND Flash Errata
Description : Some of AC characteristics are not meeting the specification.
> AC characteristics : Refer to Table
Affected Products : K9F1208Q0A-XXB0, K9F1216Q0A-XXB0
K9F5608Q0C-XXB0, K9F5616Q0C-XXB0
K9K1208Q0C-XXB0, K9K1216Q0C-XXB0
Improvement schedule : The components without this restriction will
be available from work week 23 or after.
Workaround : Relax the relevant timing parameters according to the table.
Table
UNIT : ns
Parameters
tWC tWH tWP tRC tREH tRP tREA tCEA
Specification
45 15 25 50 15 25 30 45
Relaxed Condition 80 20 60 80 20 60 60 75
Sincerely,
Product Planning & Application Eng.
Memory Division
Samsung Electronics Co.
1




K9F5608Q0C-H pdf, 반도체, 판매, 대치품
K9F5608U0C-VCB0,VIB0,FCB0,FIB0
K9F5608Q0C-DCB0,DIB0,HCB0,HIB0
K9F5608U0C-YCB0,YIB0,PCB0,PIB0
K9F5608U0C-DCB0,DIB0,HCB0,HIB0
K9F5616Q0C-DCB0,DIB0,HCB0,HIB0
K9F5616U0C-YCB0,YIB0,PCB0,PIB0
K9F5616U0C-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
X16
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
X8
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
K9F56XXU0C-YCB0,PCB0/YIB0,PIB0
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
X8 X16
N.C Vss
N.C I/O15
N.C I/O7
N.C I/O14
I/O7 I/O6
I/O6 I/O13
I/O5 I/O5
I/O4 I/O12
N.C I/O4
N.C N.C
LOCKPRE LOCKPRE
Vcc Vcc
Vss N.C
N.C N.C
N.C N.C
N.C I/O11
I/O3 I/O3
I/O2 I/O10
I/O1 I/O2
I/O0 I/O9
N.C I/O1
N.C I/O8
N.C I/O0
N.C Vss
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1 #48
#24
0~8¡Æ
0.45~0.75
0.018~0.030
18.40±0.10
0.724±0.004
#25
1.00±0.05
0.039±0.002
01.0.2407MAX
0.05
0.002
MIN
(
0.50
0.020
)
3

4페이지










K9F5608Q0C-H 전자부품, 판매, 대치품
K9F5608U0C-VCB0,VIB0,FCB0,FIB0
K9F5608Q0C-DCB0,DIB0,HCB0,HIB0
K9F5608U0C-YCB0,YIB0,PCB0,PIB0
K9F5608U0C-DCB0,DIB0,HCB0,HIB0
K9F5616Q0C-DCB0,DIB0,HCB0,HIB0
K9F5616U0C-YCB0,YIB0,PCB0,PIB0
K9F5616U0C-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
PIN DESCRIPTION
Pin NAME
I/O0 ~ I/O7
(K9F5608X0C)
I/O0 ~ I/O15
(K9F5616X0C)
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
COMMAND LATCH ENABLE
CLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
CE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’Page read’section of Device operation .
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
WP
The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage
generator is reset when the WP pin is active low. When LOCKPRE is a logic high and WP is a logic low, the
all blocks go to lock state.
READY/BUSY OUTPUT
R/B
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
VCCQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss GROUND
N.C
NO CONNECTION
Lead is not internally connected.
DNU
DO NOT USE
Leave it disconnected
LOCKPRE
LOCK MECHANISM & POWER-ON AUTO-READ ENABLE
To Enable and disable the Lock mechanism and Power On Auto Read. When LOCKPRE is a logic high,
Block Lock mode and Power-On Auto-Read mode are enabled, and when LOCKPRE is a logic low, Block
Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only on
3.3V device(K9F56XXU0C)
Don’t leave it N.C. Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
6

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