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K9F5608U0B-HCB0 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K9F5608U0B-HCB0은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 K9F5608U0B-HCB0 자료 제공

부품번호 K9F5608U0B-HCB0 기능
기능 32M x 8 Bit / 16M x 16 Bit NAND Flash Memory
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


K9F5608U0B-HCB0 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



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K9F5608U0B-HCB0 데이터시트, 핀배열, 회로
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 Initial issue.
Draft Date
May. 15th 2001
0.1 At Read2 operation in X16 device
: A3 ~ A7 are Don’t care ==> A3 ~ A7 are "L"
Sep. 20th 2001
0.2 1. IOL(R/B) of 1.8V device is changed.
Nov. 5th 2001
-min. Value: 7mA -->3mA
-typ. Value: 8mA -->4mA
2. AC parameter is changed.
tRP(min.) : 30ns --> 25ns
3. WP pin provides hardware protection and is recommended to be kept
at VIL during power-up and power-down and recovery time of minimum
1µs is required before internal circuit gets ready for any command
sequences as shown in Figure 15.
---> WP pin provides hardware protection and is recommended to be
kept at VIL during power-up and power-down and recovery time of
minimum 10µs is required before internal circuit gets ready for any
command sequences as shown in Figure 15.
0.3 1. X16 TSOP1 pin is changed.
: #36 pin is changed from VccQ to N.C .
Feb. 15th 2002
0.4
1. In X16 device, bad block information location is changed from 256th
byte to 256th and 261th byte.
Apr. 15th 2002
2. tAR1, tAR2 are merged to tAR.(page 12)
(before revision) min. tAR1 = 20ns , min. tAR2 = 50ns
(after revision) min. tAR = 10ns
3. min. tCLR is changed from 50ns to 10ns.(page12)
4. min. tREA is changed from 35ns to 30ns.(page12)
5. min. tWC is changed from 50ns to 45ns.(page12)
6. Unique ID for Copyright Protection is available
-The device includes one block sized OTP(One Time Programmable),
which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by
contact with Samsung.
7. tRHZ is divide into tRHZ and tOH.(page 12)
- tRHZ : RE High to Output Hi-Z
- tOH : RE High to Output Hold
8. tCHZ is divide into tCHZ and tOH.(page 12)
- tCHZ : CE High to Output Hi-Z
- tOH : CE High to Output Hold
Remark
Advance
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1




K9F5608U0B-HCB0 pdf, 반도체, 판매, 대치품
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
X16
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
X8
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
K9F56XXU0B-YCB0,PCB0/YIB0,PIB0
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
X8
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
X16
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
N.C
N.C
Vcc
N.C
N.C
N.C
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1 #48
#24
0~8¡Æ
0.45~0.75
0.018~0.030
18.40±0.10
0.724±0.004
#25
1.00±0.05
0.039±0.002
01.0.2407MAX
0.05
0.002
MIN
(
0.50
0.020
)
4

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K9F5608U0B-HCB0 전자부품, 판매, 대치품
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
(K9F5608X0B)
I/O0 ~ I/O15
(K9F5616X0B)
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
COMMAND LATCH ENABLE
CLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
CE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’Page read’section of Device operation.
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
WP The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
R/B
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
VCCQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss GROUND
N.C
NO CONNECTION
Lead is not internally connected.
GND
GND INPUT FOR ENABLING SPARE AREA
To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state.
DNU
DO NOT USE
Leave it disconnected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
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부품번호상세설명 및 기능제조사
K9F5608U0B-HCB0

32M x 8 Bit / 16M x 16 Bit NAND Flash Memory

Samsung semiconductor
Samsung semiconductor

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