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K9K1208U0C 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K9K1208U0C은 전자 산업 및 응용 분야에서
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부품번호 K9K1208U0C 기능
기능 64M x 8 Bit / 32M x 16 Bit NAND Flash Memory
제조업체 Samsung semiconductor
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K9K1208U0C 데이터시트, 핀배열, 회로
K9K1208U0A-YCB0, K9K1208U0A-YIB0
Document Title
64M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No History
Draft Date Remark
0.0 1. Initial issue
Dec. 6th 2000 Preliminary
- Changed /SE(pin # 6, Spare Area Enable) pin to N.C ( No Connection).
So, /SE pin is don’t-cared regardless of external logic input level and is
fixed as low internally.
0.1 1. Changed plane address in Copy-Back Program
Dec. 28th 2000
- A14, the plane address, of source and destination page address must be
the same. => A14 and A25, the plane address, of source and destination
page address must be the same.
0.2 1. In addition, explain WE function in pin description
- The WE must be held high when outputs are activated.
Jan. 17th 2001 Final
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1




K9K1208U0C pdf, 반도체, 판매, 대치품
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
PRODUCT INTRODUCTION
The K9K1208U0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed by two NAND structures, totaling 8,448 NAND structures of 16 cells. The array organization is shown in Figure 2.
The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The mem-
ory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9K1208U0A.
The K9K1208U0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same four address
cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device
operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the
K9K1208U0A.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read 1
00h/01h(1)
-
Read 2
50h -
Read ID
90h -
Reset
FFh -
O
Page Program
80h 10h
Block Erase
60h D0h
Read Status
70h -
O
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half
register(00h) on the next cycle.
4

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K9K1208U0C 전자부품, 판매, 대치품
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
NVB
Min
4,026
Typ.
-
Max
4,096
Unit
Blocks
NOTE :
1. The K9K1208U0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try
to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
AC TEST CONDITION
(K9K1208U0A-YCB0 :TA=0 to 70°C, K9K1208U0A-YIB0:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load (3.0V +/-10%)
1 TTL GATE and CL=50pF
Output Load (3.3V +/-10%)
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
CI/O
CIN
Test Condition
VIL=0V
VIN=0V
Min
-
-
Max
30
30
Unit
pF
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
WE
RE
WP
Mode
HL L
LHL
HX
Command Input
Read Mode
HX
Address Input(4clock)
HL L
LHL
HH
Command Input
Write Mode
HH
Address Input(4clock)
LLL
H H Data Input
L L LH
X sequential Read & Data Output
L L L H H X During Read(Busy)
X X X X X H During Program(Busy)
X X X X X H During Erase(Busy)
X X(1) X X X L Write Protect
X X H X X 0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Program Time
tPROG
-
200 500
Number of Partial Program Cycles
in the Same Page
Main Array
Spare Array
Nop
-
-
-
-
2
3
Block Erase Time
tBERS
-
2
3
Unit
µs
cycles
cycles
ms
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관련 데이터시트

부품번호상세설명 및 기능제조사
K9K1208U0A-YCB0

64M x 8 Bit NAND Flash Memory

Samsung semiconductor
Samsung semiconductor
K9K1208U0A-YCB0

64M x 8 Bit NAND Flash Memory

Samsung semiconductor
Samsung semiconductor

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