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K9K1G08U0M-YIB0 데이터시트 PDF




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부품번호 K9K1G08U0M-YIB0 기능
기능 128M x 8 Bit NAND Flash Memory
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K9K1G08U0M-YIB0 데이터시트, 핀배열, 회로
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Document Title
128M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No History
0.0 1. Initial issue
0.1 1.[Page 31] device code (76h) --> device code (79h)
0.2 1.Powerup sequence is added
: Recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences
Draft Date Remark
Apr. 7th 2001
Jul. 3rd 2001
Jul. 23th 2001
2.5V
VCC
High
WP
2.5V
WE 1µ
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. [Page28] Only address A 14 to A25 is valid while A9 to A13 is ignored
--> Only address A14 to A26 is valid while A 9 to A13 is ignored
0.3 (page 30)
A14 and A15 must be the same between source and target page
Sep. 13th 2001
--> A14 , A15 and A26 must be the same between source and target page
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1




K9K1G08U0M-YIB0 pdf, 반도체, 판매, 대치품
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Product Introduction
The K9K1G08U0M is a 1,026Mbit(1,107,296,436 bit) memory organized as 262,144 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed by two NAND structures, totaling 16,384 NAND structures of 16 cells. The array organization is shown in Figure 2.
The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 8,192 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9K1G08U0M.
The K9K1G08U0M has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 128M byte physical space
requires 27 addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row
address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In
Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific c om-
mands into the command register. Table 1 defines the specific commands of the K9K1G08U0M.
The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into eight 128Mbit
separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining
the conventional 512 byte structure.
The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of
selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burst-
reading and data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Function
Read 1
Read 2
Read ID
Reset
Page Program (True)(2)
Page Program (Dummy)(2)
Copy-Back Program(True)(2)
Copy-Back Program(Dummy) (2)
Block Erase
Multi-Plane Block Erase
Read Status
Read Multi-Plane Status
1st. Cycle
00h/01h (1)
50h
90h
FFh
80h
80h
00h
03h
60h
60h----60h
70h
71h(3)
2nd. Cycle
-
-
-
-
10h
11h
8Ah
8Ah
D0h
D0h
-
-
3rd. Cycle
-
-
-
-
-
-
10h
11h
-
-
-
-
Acceptable Command
during Busy
O
O
O
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation.
Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation.
3. The 71h command should be used for read status of Multi Plane operation.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
4

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K9K1G08U0M-YIB0 전자부품, 판매, 대치품
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Temperature Under Bias
Storage Temperature
K9K1G08U0M-YCB0
K9K1G08U0M-YIB0
Symbol
VIN
VCC
TBIAS
TSTG
Rating
-0.6 to + 4.6
-0.6 to + 4.6
-10 to +125
-40 to +125
-65 to +150
Unit
V
°C
°C
NOTE:
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC, +0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
(Voltage reference to GND, K9K1G08U0M-YCB0 :TA=0 to 70°C, K9K1G08U0M-YIB0:TA=-40 to 85°C)
Parameter
Symbol
Min
Typ.
Max
Supply Voltage
VCC 2.7 3.3 3.6
Supply Voltage
VSS
0
0
0
Unit
V
V
Dc and Operating Characteristics (Recommended operating conditions otherwise noted.)
Parameter
Symbol
Test Conditions
Min Typ
Max
Operating Sequential Read
Current Program
ICC1
ICC2
tRC=50ns, CE = VIL, IOUT=0mA
-
- 10
- 10
30
30
Erase
ICC3
-
- 10
30
Stand-by Current(TTL)
ISB1 CE=VIH, WP= 0V/V CC
--
1
Stand-by Current(CMOS)
ISB2 CE=VCC-0.2, WP = 0V/V CC
- 10
50
Input Leakage Current
ILI VIN=0 to 3.6V
- - ±10
Output Leakage Current
ILO VOUT=0 to 3.6V
- - ±10
Input High Voltage
VIH - 2.0 - VCC+0.3
Input Low Voltage, All inputs
VIL
-
-0.3 -
0.8
Output High Voltage Level
VOH IOH=-400µA
2.4 -
-
Output Low Voltage Level
VOL IOL=2.1mA
--
0.4
Output Low Current(R/B)
IOL(R/B) VOL=0.4V
8 10
-
Unit
mA
µA
V
mA
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부품번호상세설명 및 기능제조사
K9K1G08U0M-YIB0

128M x 8 Bit NAND Flash Memory

Samsung semiconductor
Samsung semiconductor
K9K1G08U0M-YIB0

128M x 8 Bit NAND Flash Memory

Samsung semiconductor
Samsung semiconductor

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