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부품번호 | K9K1G16Q0A 기능 |
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기능 | 128M x 8 Bit / 64M x 16 Bit NAND Flash Memory | ||
제조업체 | Samsung semiconductor | ||
로고 | |||
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Document Title
128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
Preliminary
FLASH MEMORY
Revision History
Revision No. History
0.0 Initial issue.
0.1 1. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
2. 63FBGA,1.8V product is added.
K9K1GXXQ0A-GCB0,GIB0,JCB0,JIB0
0.2
Errata is deleted.
AC parameters are changed.
tWC tWH tWP tRC tREH tRP tREA tCEA
Before 45 15 25 50 15 25 30 45
After 60 20 40 60 20 40 40 55
Draft Date Remark
Mar. 17th 2003 Preliminary
Jun. 4th 2003 Preliminary
Aug. 1st 2003
Preliminary
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Preliminary
FLASH MEMORY
PIN CONFIGURATION (FBGA)
K9K1GXXX0A-GCB0,JCB0/GIB0,JIB0
X8 X16
12 3 4 5 6
12 3 4 5 6
N.C N.C
N.C N.C
A N.C
B
C
D
E
F
G
H
N.C N.C
/WP ALE Vss /CE /WE R/B
NC /RE CLE NC NC NC
NC NC NC NC NC NC
NC NC NC NC NC NC
NC NC NC NC NC NC
NC I/O0 NC NC NC Vcc
NC I/O1 NC VccQ I/O5 I/O7
Vss I/O2 I/O3 I/O4 I/O6 Vss
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C
A
B
C
D
E
F
G
H
N.C N.C
/WP ALE Vss /CE /WE R/B
NC /RE CLE NC NC NC
NC NC NC NC NC NC
NC NC NC NC NC NC
NC NC NC I/O5 I/O7 NC
I/O8 I/O1 I/O10 I/O12 IO14 Vcc
I/O0 I/O9 I/O3 VccQ I/O6 I/O15
Vss I/O2 I/O11 I/O4 I/O13 Vss
N.C N.C
N.C N.C
N.C N.C
N.C N.C
Top View
Top View
4
4페이지 K9K1G08Q0A K9K1G16Q0A
K9K1G08U0A K9K1G16U0A
Figure 1-1. Functional Block Diagram
VCC
VSS
A9 - A26
X-Buffers
Latches
& Decoders
A0 - A7
Y-Buffers
Latches
& Decoders
Command
A8
Command
Register
CE Control Logic
RE & High Voltage
WE Generator
CLE ALE WP
Figure 2-1. Array Organization
Preliminary
FLASH MEMORY
1,024M + 32M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 262,144
Page Register & S/A
Y-Gating
I/O Buffers & Latches
VCC
VSS
Global Buffers
Output
Driver
I/0 0
I/0 7
1 Block = 32 Pages
(16K + 512) Byte
256K Pages
(=8,192 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
512B Bytes
16 Bytes
1 Page = 528 Bytes
1 Block = 528 B x 32 Pages
= (16K + 512) Bytes
1 Device = 528B x 32Pages x 8,192 Blocks
= 1,056 Mbits
8 bit
Page Register
512 Bytes
I/O 0 ~ I/O 7
16 Bytes
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A9
A10 A11 A12 A13 A14 A15
3rd Cycle A17 A18 A19 A20 A21 A22 A23
4th Cycle A25
A26
*L
*L
*L
*L
*L
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
I/O 7
A7
A16
A24
*L
Column Address
Row Address
(Page Address)
7
7페이지 | |||
구 성 | 총 30 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
K9K1G16Q0A | 128M x 8 Bit / 64M x 16 Bit NAND Flash Memory | Samsung semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |