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PDF SM9403BM Data sheet ( Hoja de datos )
| Número de pieza | SM9403BM | |
| Descripción | DVDRAM Servo-amplifier LSI | |
| Fabricantes | Nippon Precision Circuits Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SM9403BM (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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NIPPON PRECISION CIRCUITS INC.
SM9403BM
DVDRAM Servo-amplifier LSI
OVERVIEW
The SM9403BM is a DVDROM and DVDRAM servo preprocessor LSI, designed for double-speed format
DVDROM and DVDRAM drives.
The SM9403BM is fabricated using a BiCMOS process, and incorporates an analog signal processing circuit
that generates signals needed by the digital servo processor, a DPD signal processing circuit (DVDROM), and
a CAPA (Complementary Allocated Pit Address) detection circuit (DVDRAM) all in a single chip. It operates
from a single 5 V supply, and is available in 36-pin plastic SSOP packages.
FEATURES
s DPD signal processor
s Tracking error signal output
s Focus error signal output
s Tracking error signal sample-and-hold
s Focus error signal sample-and-hold
s CAPA detection function
s Track count pulse generator
s Off-track detection
s 2V and 4V reference voltage generator
s Serial interface for setting internal parameters
s Sleep-mode function
s Single 5 V supply
s 36-pin plastic SSOP
APPLICATIONS
s Double-speed DVDROM drives
s Double-speed DVDRAM drives
ORDERING INFORMATION
Device
SM9403BM
Package
36-pin SSOP
PINOUT
36-pin SSOP (Top View)
NC 1
NC 2
FER 3
FHOLD 4
FSUB 5
ISET 6
DPDD 7
DPDC 8
DPDB 9
DPDA 10
AGND 11
MMTI 12
CAPAN 13
CAPAP 14
CAPLFC 15
TSUB 16
THOLD 17
TRE 18
36 DPDG
35 DPDI
34 DEFECT
33 DGND
32 SCLK
31 SDATA
30 SENB
29 DVCC
28 CAPSEEK
27 CAPSEL
26 CAPIN
25 AVCC
24 CAPOUT
23 CAPAREA
22 TRP
21 TROFF
20 VREF2
19 VREF4
NIPPON PRECISION CIRCUITS—1
1 page  
SM9403BM
DC Electrical Characteristics
VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C
Parameter
Symbol
Condition
Rating
min typ max
Current consumption1
CAPSEEK, CAPSEL, DEFECT, SENB, SDATA,
SCLK HIGH-level input voltage
IC C 1 Operating mode
IC C 2 Sleep mode 1
IC C 3 Sleep mode 2
IC C 4 Sleep mode 3
∆IC C IC C 1 − IC C 2
V IH
–
–
–
–
9
0.8VCC
28
17
2.0
–
–
–
34
21
2.6
1.0
–
–
CAPSEEK, CAPSEL, DEFECT, SENB, SDATA,
S C L K L OW -level input voltage
V IL
– – 0.2VCC
CAPSEEK, CAPSEL, DEFECT HIGH-level input
current
IIH1 V IN = V C C
50 100 200
S E N B , SDATA, SCLK HIGH-level input current
CAPSEEK, CAPSEL, DEFECT, SENB, SDATA,
S C L K L OW -level input current
IIH2 V IN = V C C
IIL V IN = G N D
––
−3 –
3
–
C A PA R E A , C A P I N , C A P O U T, T R P, T R O F F
HIGH-level output voltage
V O H IO H = −0 . 2 m A
VCC − 0.2
–
–
C A PA R E A , C A P I N , C A P O U T, T R P, T R O F F
L OW -level output voltage
V O L 1 IO L = 0.8mA
– – 0.4
S DATA LOW -level output voltage
VOL2
IO L = 7mA
– – 1.0
1. 33kΩ resistor connected between DPDG and AG N D
47kΩ resistor connected between DPDI and AG N D
120kΩ resistor connected between MMTI and AG N D
47kΩ resistor connected between ISET and AG N D
1000pF capacitor connected between FHOLD and AGND 1000pF capacitor connected between THOLD and AGND
0.1µF capacitor connected between VREF4 and AGND
0.1µF capacitor connected between VREF2 and AGND
0.01µF capacitor connected between CAPLFC and AG N D 0.01µF capacitor connected between ISET and AG N D
C A PA P, CAPA N , D P DA , D P D B, D P D C, D P D D, FSUB, TSUB connected to VREF2 or other 2V supply.
S E N B , SDATA, SCLK connected to GND; All other pins (excluding supply and ground pins) open circuit.
Sleep mode 1: DPD system only in sleep condition.
Sleep mode 2: All blocks except reference supply voltage generator in sleep condition.
Sleep mode 3: All blocks in sleep condition.
Unit
mA
V
V
µA
µA
µA
V
V
V
NIPPON PRECISION CIRCUITS—5
5 Page 
SM9403BM
FUNCTIONAL DESCRIPTION
Serial Interface
The SM9403BM uses a serial interface comprising 5
ports to control and set all functions. The address and
bit configuration of each port is shown in table 1
Table 1. Port address and bit configuration1
Bit number
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Data Address
MSB LSB
DPE HAE FFE TFE SWB SWA SL2 SL1 × LOW LOW LOW HIGH LOW ×
×
OF3 OF2 OF1 WD2 WD1 HS3 HS2 HS1 × LOW LOW LOW HIGH HIGH ×
×
THE FHE HRE MM2 MM1 LS3 LS2 LS1 × LOW LOW HIGH LOW LOW ×
×
EQE CG3 CG2 CG1 DL4 DL3 DL2 DL1 × LOW LOW HIGH LOW HIGH ×
×
TS3 TS2 TS1 –
–
– DG2 DG1 × LOW LOW HIGH HIGH LOW ×
×
1. × = don’t care, – = unassigned
Serial data is input on SDATA with the LSB first, in
sync with the falling edge of the SCLK clock. After
the 16th SCLK falling edge and 16 bits of valid data
has been input, the SDATA n-channel open-drain
output goes LOW as an acknowledge signal.
If the number of SCLK cycles which occur when
SENB (serial interface enable) is HIGH is less than
16, the received data is ignored and the internal port
is not updated. If the number of SCLK cycles is
greater than 16, the data is still considered value up
to the 16th SCLK falling edge, the data is latched
into the internal port, and the acknowledge signal is
output. The acknowledge signal is held until SENB
goes LOW again.
Focus Sample-and-Hold/Low-pass Filter (FSUB → FER)
This stage, the signal which is generated from the
header position detector signal samples and holds the
focus error signal. The output then passes through a
low-pass filter. This low-pass filter can be turned ON
or OFF using the serial interface control bit FFE.
Table 2. Focus low-pass filter ON/OFF control
FFE Low-pass filter1
LOW ON
HIGH
OFF
1. Default is ON
Tracking Sample-and-Hold/Low-pass Filter (TSUB → TRE)
This stage, the signal which is generated from the
header position detector signal samples and holds the
tracking error signal. The output then passes through
a low-pass filter. This low-pass filter cutoff frequency
can be switched using the serial interface control bit
TFE.
Table 3. Tracking low-pass filter cutoff frequency
TFE Low-pass filter1
LOW
HIGH
1. Default is 160kHz
fC = 160kHz
fC = 35kHz
NIPPON PRECISION CIRCUITS—11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SM9403BM.PDF ] | |
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