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PDF SIW3500 Data sheet ( Hoja de datos )
| Número de pieza | SIW3500 | |
| Descripción | ULTIMATEBLUE | |
| Fabricantes | RF Micro Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SIW3500 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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Preliminary
0
SiW3500
ULTIMATEBLUE
Features
• RF System on Chip (SoC) for
Bluetooth wireless technology
combining a 2.4 GHz transceiver,
baseband processor, and protocol
stack ROM.
• Bluetooth specification V1.2 qualified
including mandatory and optional
functions such as AFH and eSCO.
• Manufactured using standard
0.18-micron CMOS process
technology.
• UART based Host Control Interface
(HCI) transport layer supports
standard and 3-wire modes.
• Direct conversion RF architecture
improves receiver-blocking
performance.
• I/O voltage supply can range from
1.62 V to 3.63 V.
• -85 dBm receiver sensitivity and
+2 dBm transmitter power typical
performance specifications.
• Integrated analog and digital voltage
regulators simplify system design.
• 50 Ω RF I/O does not need any
additional external impedance
matching components.
• Flexible reference clock source
options including crystal or direct
input from the host platform.
• Internal temperature compensated
transmitter and receiver circuits
deliver consistent performance from
-40° to +85°C.
• On-chip ROM software storage with
patch capability.
Applications
• Mobile phones and smart phones.
• Bluetooth audio headset.
• Bluetooth hands-free kit.
RF_I/O
PLL
Control
Clock Distribution
LNA
Internal
50-Ohm
Match
Network
PLL
Synthesizer
Power
Control
Aux ADC
DRIVER
0
90
0
90
Voltage Regulators and
Power Distribution
ADC
Optional flash interface
ARM7TDMI®
Processor
UART
ADC
DAC
GFSK
Modem
Bluetooth
Link
Controller
Data SRAM
Multi Function
I/Os
DAC
Firmware ROM
Audio CODEC
Interface
Block Diagram
Product Description
The UltimateBlue SiW3500™ is a RF System On Chip (SoC) that combines
a 2.4 GHz transceiver, baseband processor, and protocol stack software for
Bluetooth® wireless technology. Due to its low power CMOS process, the
SiW3500 is ideally suited for applications such as mobile phones, audio
headsets, and other embedded products.
The SiW3500 integrates an ARM7TDMI processor for software execution
from either internal ROM or external FLASH memory. The standard
SiW3500 ROM contains the Bluetooth lower layer stack software including
the HCI transport driver.
The SiW3500 is packaged in a 6 x 6 Pb-Free 96-VFBGA that meets RoHS
(Green) requirements. Known Good Die (KGD) is available for special
applications.
Optimum Technology Matching® Applied
Si BJT
Si Bi-CMOS
9GaAs HBT
SiGe HBT
GaAs MESFET
Si CMOS
GaInP/HBT
GaN HEMT
SiGe Bi-CMOS
60 0066 R00Hrf SiW3500 Radio Processor DS
November 8, 2004
Ordering Information
SiW3500
UltimateBlue
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
14-37
1 page  
Preliminary
SiW3500
EEPROM is not required for configurations with external flash. The EEPROM is the non-volatile memory (NVM) in the
system and contains the system configuration parameters such as the Bluetooth device address, the CODEC type, as
well as other parameters. These default parameters are set at the factory, and some parameters will change depending
on the system configuration. Optionally, the memory parameters can be downloaded from the host processor at boot up
eliminating the need for EEPROM. Please consult the Application Support team for details. The EEPROMs should have
a serial I2C interface with a minimum size of 2 Kbits and 16-byte page write buffer capabilities.
General System Requirements
System Reference Clock
The SiW3500 chip can use either an external crystal or a reference clock as the system clock input. A partial list of
supported frequencies (in MHz) includes: 9.6, 12, 12.8, 13, 14.4, 15.36, 16, 16.8, 19.2, 19.68, 19.8, 26, 32, 38.4, and 48.
For other frequencies, please contact Applications Support. The system reference crystal/clock must have an accuracy
of ±20 PPM or better to meet the Bluetooth specification.
Low Power Clock
For the Bluetooth low power clock, a 32.768 kHz crystal can be used to drive the SiW3500 oscillator circuit, or alterna-
tively, a 32.768 kHz reference clock signal can be used instead of a crystal. If the lowest power consumption is not
required during low-power modes such as sniff, hold, park, and idle modes, the 32.768 kHz crystal may be omitted in the
design.
If the 32.768 kHz clock source is used, the clock source should be connected to the CLK32_IN pin and must meet the
following requirements:
• For AC-coupled via 100 pF or greater (peak-to-peak voltage):
400 mVP-P < CLK32_IN < VDD_C
• For DC-coupled:
CLK32_IN minimum peak voltage < VIL
CLK32_IN maximum peak voltage > VIH
Where VIL = 0.3 * VDD_C
Where VIH = 0.7 * VDD_C
• For both cases, the signal is not to exceed:
-0.3 V < CLK32_IN < VDD_C + 0.3 V
Power Supply Description
The SiW3500 operates at 1.8 V core voltage for internal analog and digital circuits. The chip has internal analog and
digital voltage regulators simplifying power supply requirements to the chip. The internal voltage regulators can be
supplied directly from a battery or from other system voltage sources. Optionally, the internal regulators can be by-
passed if 1.8 V regulated source is available on the system.
Function
Regulator input pin
Regulator output pin
Internal Regulator Used
Internal Analog Regulator
VBATT_ANA = 2.3 to 3.63 V
VCC_OUT = 1.8 V
Internal Digital Regulator
VBATT_DIG = 2.3 to 3.63 V
VDD_C = 1.8 V
Function
Analog Core Circuits
Circuit voltage supply pin
VCC = 1.8 V
Internal Regulator Bypassed
Digital Core Circuits
VDD_C = 1.8 V
Note: Both regulators can be bypassed if external regulation is desired. When bypassing the analog regulator, the VBATT_ANA and VCC_OUT pins
must be tied together and the external analog voltage (1.8 V) should be applied to the VBATT_ANA pin. When bypassing the digital regulator, the
VBATT_DIG pin should be left unconnected and the external digital voltage (1.8 V) should be applied to VBB_OUT pin.
The power for the I/Os is taken from two separate sources (VDD_P and VDD_P_ALT). They can range from 1.62 to 3.63
60 0066 R00Hrf SiW3500 Radio Processor DS
14-41
5 Page 
Preliminary
SiW3500
Current Consumption (TOP=+25°C, VBATT=3.0V using internal regulators)
Operating Mode
Average Max
Unit
Standby
40 80 µA
Continuous transmit*
48 55 mA
Continuous receive*
54 60 mA
Parked slave, 1.28 sec. interval
90 – µA
Inquiry scan, 1.28 sec interval
440 –
µA
Page scan, 1.28 sec. interval
560 –
µA
ACL connection, sniff mode, 40 ms interval
1.3 – mA
ACL data transfer 723 kbps TX, 57 kbps RX
42 – mA
SCO connection, HV3 packets
22 – mA
*Note: Continuous transmit and receive currents are measured in operating modes where there is no activity in baseband digital circuits.
Digital Regulator Specification (TOP = 25°C)
Parameter
Description
Min Typ Max Unit
Output voltage
(I OUT = 10 mA)
1.62 1.80 1.98
V
Line regulation
(I OUT = 0 mA, VBATT_DIG = 2.3 V to 3.63 V)
– 8.0 – mV
Load regulation (I OUT = 3 mA to 80 mA)
– 9.0 – mV
Dropout voltage (I OUT = 10 mA)
– – 250 mV
Output maximum
current
Maximum supplied current while maintaining regulation
–
– 80 mA
Quiescent current Off current
– 10
– µA
Ripple rejection
f RIPPLE = 400 Hz
– 40
– dB
Radio Specification
Parameter
VCO Operating
Range
Frequency
PLL lock time
Average tune time
Description
Min Typ Max
2402 – 2480
– 60 100
Receiver Specification1 (VBATT=3.3V, VCC=internal analog regulator output, TOP = 25°C)
Parameter
Description
Min Typ Max
Receiver sensitivity BER < 0.1%
– -85 -78
Maximum
usable signal
C/I co-channel
(0.1% BER)
BER < 0.1%
Co-channel selectivity
-10 0
–
– +8.0 +10.0
C/I 1 MHz
(0.1% BER)
Adjacent channel selectivity
– -4.0 -3.0
C/I 2 MHz
(0.1% BER)
C/I ≥ 3 MHz
(0.1% BER)
2nd adjacent channel selectivity
3rd adjacent channel selectivity
Fc/3
–
-38.0
-35.0
–
-43.0
-40.0
-23 –
–
Fc/2
-25 –
–
Out-of-band
blocking2
2 * Fc/3
30 MHz - 2000 MHz
2000 MHz - 2399 MHz
2498 MHz - 3000 MHz
-45 –
-10 –
-27 –
-27 –
–
–
–
–
3000 MHz - 12.75 GHz
-10 –
–
Unit
MHz
µs
Unit
dBm
dBm
dB
dB
dB
dB
dBm
dBm
dBm
dBm
dBm
dBm
dBm
60 0066 R00Hrf SiW3500 Radio Processor DS
14-47
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SIW3500.PDF ] | |
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