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SK100E016 데이터시트 PDF




Semtech Corporation에서 제조한 전자 부품 SK100E016은 전자 산업 및 응용 분야에서
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부품번호 SK100E016 기능
기능 8-Bit Synchronous Binary Up Counter
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SK100E016 데이터시트, 핀배열, 회로
HIGH-PER.ORMANCE PRODUCTS
Description
.eatures
SK10/100E016
8-Bit Synchronous
Binary Up Counter
The SK10/100E016 is a high-speed synchronous, • 700 MHz Min Count Frequency
presettable, cascadable 8-bit binary counter.
• 1000 ps CLK to Q, TC*
• Internal TC* Feedback (Gated)
The counter features internal feedback of TC*, gated by • 8-Bit
the TCLD (terminal count load) pin. When TCLD is LOW • Fully Synchronous Counting and TC* Generation
(or left open, in which case it is pulled LOW by the internal • Asynchronous Master Reset
pull-downs), the TC* feedback is disabled, and counting • Internal 75 kInput Pulldown Resistors
proceeds continuously, with TC* going LOW to indicate • Extended 100E VEE Range of –4.2V to –5.46V
an all-one state. When TCLD is HIGH, the TC* feedback • Fully Compatible with MC10/100E016
causes the counter to automatically reload upon TC* = • Available in 28-Pin PLCC Package
LOW, thus functioning as a programmable counter. The • ESD Protection of >4000V
Qn outputs do not need to be terminated for the count
function to operate properly. To minimize noise and
power, unused Q outputs should be left unterminated.
.unctional Block Diagram
8 Bit Binary Counter - Logic Counter
Q0
PE
TCLD
QOM
CE*
MASTER
SLAVE
CE*
BIT 0
QOM*
Q0*
PO P1
MR
CLK
Q1
BIT 1
CE*
Q0*
Q1*
Q2*
Q3*
Q4*
Q5*
Q6*
P7
BITS 2-6
5
Q7
BIT 7
TC*
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation
delays as many gate functions are achieved internally without incurring a full gate delay.
Revision 1/.ebruary 13, 2001
1
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SK100E016 pdf, 반도체, 판매, 대치품
SK10/100E016
HIGH-PER.ORMANCE PRODUCTS
Application Information (continued)
LOAD
®Q0 Q7
CE* PE*
E016
LSB
®Q0 Q7
CE* PE*
E016
®Q0 Q7
CE* PE*
E016
CLK TC*
®P0 P7
CLK TC*
®P0 P7
EL01
CLK TC*
®P0 P7
CLOCK
Figure 3. 32-Bit Cascaded E016 Counter
EL01
®Q0 Q7
CE* PE*
E016
MSB
CLK TC*
®P0 P7
Programmable Divider
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider.
The TCLD pin (load on terminal count) when asserted
reloads the data present at the parallel input pin (Pns)
upon reaching terminal count (an all 1s state on the
outputs). Because this feedback is built internal to the
chip, the programmable division operation will run at very
nearly the same frequency as the maximum counting
frequency of the device. Figure 4 below illustrates the
input conditions necessary for utilizing the E016 as a
programmable divider set up to divide by 113.
HL L LHHHH
P7 P6 P5 P4 P3 P2 P1 P0
H PE*
L CE*
H TCLD
CLK TC*
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Figure 4. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
Revision 1/.ebruary 13, 2001
4
Pns = 256 113 = 8F16 = 1000 1111
where:
PO = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure
4 will result in the waveforms of Figure 5. Note that
the TC* output is used as the divide output and the
pulse duration is equal to a full clock period. For
even divide ratios, twice the desired divide ratio can
be loaded into the E016, and the TC* output can
feed the clock input of a toggle flip-flop to create a
signal divided as desired with a 50% duty cycle.
Divide
Ratio
2
3
4
5
l
l
112
113
114
l
l
254
255
256
Preset Data Inputs
P7 P6 P5 P4 P3 P2 P1 P0
HHHHHHHL
HHHHHHL H
HHHHHHL L
HHHHHL HH
llllllll
llllllll
HL LHL L L L
HL L L HHHH
HL L L HHHL
llllllll
llllllll
L L L L L LHL
LLLLLLLH
LLLLLLLL
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SK100E016 전자부품, 판매, 대치품
HIGH-PER.ORMANCE PRODUCTS
Package Information
Y BRK
N
PINLDescriptions
D
M
SK10/100E016
B 0.007 (0.180) M T L - M S N S
U
Z
0.007 (0.180) M T L - M S N S
+
WD
V
28 1
A 0.007 (0.180) M T L M S N S
Z
R 0.007 (0.180) M T L M S N S
C
E
G
G1
0.010 (0.250) S T L M S N S
0.004 (0.100)
J TSEATING PLANE
VIEW S
NOTES:
1. Datums -L-, -M-, and -N- determined where top of lead
shoulder exits plastic body at mold parting line.
2. DIM G1, true position to be measured at Datum -T-,
Seating Plane.
3. DIM R and U do not include mold flash. Allowable
mold flash is 0.010 (0.250) per side.
4. Dimensioning and tolerancing per ANSI Y14.5M,
1982.
5. Controlling Dimension: Inch.
6. The package top may be smaller than the package
bottom by up to 0.012 (0.300). Dimensions R and U
are determined at the outermost extremes of the
plastic body exclusive of mold flash, tie bar burrs,
gate burrs and interlead flash, but including any
mismatch between the top and bottom of the plastic
body.
7. Dimension H does not include Dambar protrusion or
intrusion. The Dambar protrusion(s) shall not cause
the H dimension to be greater than 0.037 (0.940).
The Dambar intrusion(s) shall not cause the H
dimension to be smaller than 0.025 (0.635).
Revision 1/.ebruary 13, 2001
+
X G1 0.010 (0.250) S T L - M S N S
H 0.007(0.180) M T L M S N S
K1
K
F 0.007 (0.180) M T L M S N S
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.485 0.495 12.32 12.57
B 0.485 0.495 12.32 12.57
C
0.165 0.180 4.20
4.57
E
0.090 0.110 2.29
2.79
.
0.013 0.019 0.33
0.48
G 0.050 BSC
1.27 BSC
H
0.026 0.032 0.66
0.81
J 0.020 --
0.51
--
K 0.025 --
0.64
--
R 0.450 0.456 11.43 11.58
U 0.450 0.456 11.43 11.58
V
0.042 0.048 1.07
1.21
W
0.042 0.048 1.07
1.21
X
0.042 0.056 1.07
1.42
Y
-- 0.020 --
0.50
Z 2o 10o 2o 10o
G1 0.410 0.430 10.42 10.92
K1 0.040
--
1.02
--
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