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PDF SK100E111PJT Data sheet ( Hoja de datos )
| Número de pieza | SK100E111PJT | |
| Descripción | 1:9 Differential Clock Driver | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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Description
.eatures
SK10/100E111
1:9 Differential
Clock Driver
PRELIMINARY
The SK10E/100E111 is a low skew 1-to-9 differential
driver designed with clock distribution in mind. It accepts
one signal input which can be either differential or single-
ended if the VBB output is used. The signal is fanned
out to 9 identical differential outputs. An enable input
is also provided. A HIGH disables the device by forcing
all Q outputs LOW and all Q* outputs HIGH.
The device is specifically designed, modeled, and
produced with low skew as the key goal. Optimal design
and layout serve to minimize gate-to-gate skew within-
device, and characterization is used to determine process
control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed
low skew device.
To ensure that the tight skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω , even if only one side is being used.
In most applications, all nine differential pairs will be
used and therefore terminated. In the case where fewer
than nine pairs are used, it is necessary to terminate at
least the output pairs on the same package side (i.e.
sharing the same VCCO) as the pair(s) being used on
that side in order to maintain minimum skew. Failure to
do this will result in small degradations of propagation
delay (on the order of 10–20ps) of the output(s) being
used which, while not being catastrophic to most designs,
will mean a loss of skew margin.
• Low Skew
• Guaranteed Skew Spec
• Differential Design
• VBB Output
• Enable Input
• Extended 100E VEE Range of –4.2 to –5.5V
• 75KΩ Internal Input Pulldown Resistors
• Fully Compatible with MC10E111 and
MC100E111
• Specified Over Industrial Temperature Range:
–40oC to 85oC
• ESD Protection of >4000V
• Available in 28-pin PLCC Package
.unctional Block Diagram
Q0
Q0*
Q1
Q1*
Q2
Q2*
Q3
Q3*
Q4
Q4*
IN
IN* Q5
Q5*
EN*
Q6
Q6*
Q7
Q7*
VBB
Q8
Q8*
Revision 1 /.ebruary 13, 2001
1
www.semtech.com
1 page  
SK10/100E111
HIGH-PER.ORMANCE PRODUCTS
AC Characteristics (continued)
IN
IN*
ts
50%
EN*
Q*
≤75 mV
Q
≤75 mV
Figure 1. Setup Time
IN
IN*
th
EN*
50%
≤75 mV
Q*
Q
≤75 mV
Figure 2. Hold Time
IN
IN*
tr
EN*
50%
Q*
Q
Figure 3. Release Time
Notes:
1. 10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
airflow greater than 500 lfpm is maintained.
2. 100E circuits are designed to meet the DC specifications shown in the table where transverse airflow
greater than 500 lfpm is maintained.
3. Differential input voltage required to obtain a full ECL swing on the outputs.
4. VCMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP(min) and 1V. The lower end of V range varies 1:1 with VEE and is equal to VEE+1.6V.
CMR
5. The differential propagation delay is defined as the delay from the crossing points of the differential
input signals to the crossing point of the differential output signals.
6. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to
the 50% point of the output signal.
7. Enable is defined as the propagation delay from the 50% point of a negative transition on EN* to the
50% point of a positive transition on Q (or a negative transition on Q). Disable is defined as the
propagation delay from the 50% point of a positive transition on EN* to the 50% point of a negative
transition on Q (or a positive transition on Q).
8. The within-device skew is defined as the worst case difference between any two similar delay paths
within a single device.
9. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to
prevent an output response greater than ±75 mV to that IN/IN transition (see Figure 1).
10. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive
going IN* to prevent an output response greater than ±75 mV to the IN/IN transition (see Figure 2).
11. The release time is the minimum time that EN must be deasserted prior to the next IN/IN* transition to
ensure an output response that meets the specified IN to Q propagation delay and output transition times
(see Figure 3).
12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the
propagation delay. The VPP(min) is AC limited for the E111 as a differential input as low as 250 mV
will still produce full ECL levels at the output.
13. Voltages referenced to VCC = 0V.
14. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data
Sheet.
15. For part ordering descriptions, see HPP Part Ordering Information Data Sheet.
Revision 1 /.ebruary 13, 2001
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