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PDF SK100E445 Data sheet ( Hoja de datos )

Número de pieza SK100E445
Descripción 4-Bit Serial/Parallel Converter
Fabricantes Semtech Corporation 
Logotipo Semtech Corporation Logotipo



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HIGH-PER.ORMANCE PRODUCTS
Description
SK10/100E445
4-Bit Serial/Parallel Converter
.eatures
The SK10/100E445 is an integrated 4-bit serial-to-
parallel data converter. The device is designed to operate • On-Chip Clock ÷ 4 and ÷8
for NRZ data rates of up to 2.0 Gb/s. The chip generates • 2.0 Gb/s Data Rate Capability
a divide by 4 and a divide by 8 clock for both 4-bit • Differential Clock and Serial Inputs
conversion and a two chip 8-bit conversion function. The • VBB Output for Single-Ended Input Applications
conversion sequence was chosen to convert the first • Asynchronous Data Synchronization
serial bit to Q0, the second to Q1, etc.
• Mode Select to Expand to 8-Bits
• Internal 75 kInput Pulldown Resistors
Two selectable serial inputs provide a loopback capability • ESD Protection of >4000V
for testing purposes when the device is used in • Extended 100E VEE Range of –4.2V to –5.46V
conjunction with the R446 parallel to serial converter. • Fully Compatible with MC10/100E445
• Available in 28-Pin PLCC Package
The start bit for conversion can be moved using the SYNC
input. A single pulse applied asynchronously for at least
two input clock cycles shifts the start bit for conversion
from Qn to Qn–1. For each additional shift required, an
additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock
dividers to “swallow” a clock pulse, effectively shifting a
bit from the Qn to the Qn–1 output (see Timing Diagram
B).
The MODE input is used to select the conversion mode
of the device. With the MODE input LOW, or open, the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the data on the output will change
on every eighth clock cycle, thus allowing for an 8-bit
conversion scheme using two E445’s. When cascaded
in an 8-bit conversion scheme, the devices will not
operate at the 2.0 Gb/s data rate of a single device.
Refer to the applications section of this data sheet for
more information on cascading the E445.
.unctional Block Diagram
SINB
SINB*
SINA
SINA*
SEL
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
Q3
Q2
Q1
Q0
SOUT
SOUT*
For lower data rate applications, a VBB reference voltage
is supplied for single-ended inputs. When operating at
clock rates above 500 MHz, differential input signals
are recommended. For single-ended inputs, the VBB pin
is tied to the inverting differential input and bypassed
via a 0.01 µF capacitor. The VBB provides the switching
reference for the input differential amplifier. The VBB
can also be used to AC couple an input signal.
MODE
CLK
CLK*
SYNC
In Out
Latch
EN
DQ
D
1
Out
¸4
R
Out
¸2
R
CL/4
CL/4*
CL/8
CL/8*
Upon power-up, the internal flip-flops will attain a random
state. To synchronize multiple E445’s in a system, the
master reset must be asserted.
RESET
Q*
Revision 1/.ebruary 21, 2001
1
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SK100E445 pdf
HIGH-PER.ORMANCE PRODUCTS
Package Information
Y BRK
N
D
PILNDescriptions
M
SK10/100E445
B 0.007 (0.180) M T L - M S N S
U
Z
0.007 (0.180) M T L - M S N S
+
WD
V
28 1
+
X
G1
0.010 (0.250) S T L - M S N S
A 0.007 (0.180) M T L – M S N S
Z
R 0.007 (0.180) M T L M S N S
C
E
G
G1
0.010 (0.250) S T L M S N S
0.004 (0.100)
J TSEATING PLANE
VIEW S
NOTES:
1. Datums -L-, -M-, and -N- determined where top of lead
shoulder exits plastic body at mold parting line.
2. DIM G1, true position to be measured at Datum -T-,
Seating Plane.
3. DIM R and U do not include mold flash. Allowable mold flash
is 0.010 (0.250) per side.
4. Dimensioning and tolerancing per ANSI Y14.5M, 1982.
5. Controlling Dimension: Inch.
6. The package top may be smaller than the package bottom by
up to 0.012 (0.300). Dimensions R and U are determined at
the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the
plastic body.
7. Dimension H does not include Dambar protrusion or
intrusion. The Dambar protrusion(s) shall not cause the H
dimension to be greater than 0.037 (0.940). The Dambar
intrusion(s) shall not cause the H dimension to be smaller
than 0.025 (0.635).
H 0.007(0.180) M T L M S N S
K1
VIEW S
K
F 0.007 (0.180) M T L M S N S
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.485 0.495 12.32 12.57
B 0.485 0.495 12.32 12.57
C
0.165 0.180 4.20
4.57
E
0.090 0.110 2.29
2.79
.
0.013 0.019 0.33
0.48
G 0.050 BSC
1.27 BSC
H
0.026 0.032 0.66
0.81
J 0.020 --
0.51
--
K 0.025 --
0.64
--
R 0.450 0.456 11.43 11.58
U 0.450 0.456 11.43 11.58
V
0.042 0.048 1.07
1.21
W
0.042 0.048 1.07
1.21
X
0.042 0.056 1.07
1.42
Y
-- 0.020 --
0.50
Z 2o 10o 2o 10o
G1 0.410 0.430 10.42 10.92
K1 0.040
--
1.02
--
Revision 1/.ebruary 21, 2001
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