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SG3525A 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 SG3525A은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 SG3525A 자료 제공

부품번호 SG3525A 기능
기능 PULSE WIDTH MODULATOR CONTROL CIRCUITS
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SG3525A 데이터시트, 핀배열, 회로
SG3525A
Pulse Width Modulator
Control Circuit
The SG3525A pulse width modulator control circuit offers
improved performance and lower external parts count when
implemented for controlling all types of switching power supplies.
The on−chip +5.1 V reference is trimmed to "1% and the error
amplifier has an input common−mode voltage range that includes the
reference voltage, thus eliminating the need for external divider
resistors. A sync input to the oscillator enables multiple units to be
slaved or a single unit to be synchronized to an external system clock.
A wide range of deadtime can be programmed by a single resistor
connected between the CT and Discharge pins. This device also
features built−in soft−start circuitry, requiring only an external timing
capacitor. A shutdown pin controls both the soft−start circuitry and the
output stages, providing instantaneous turn off through the PWM latch
with pulsed shutdown, as well as soft−start recycle with longer
shutdown commands. The under voltage lockout inhibits the outputs
and the changing of the soft−start capacitor when VCC is below
nominal. The output stages are totem−pole design capable of sinking
and sourcing in excess of 200 mA. The output stage of the SG3525A
features NOR logic resulting in a low output for an off−state.
Features
8.0 V to 35 V Operation
5.1 V " 1.0% Trimmed Reference
100 Hz to 400 kHz Oscillator Range
Separate Oscillator Sync Pin
Adjustable Deadtime Control
Input Undervoltage Lockout
Latching PWM to Prevent Multiple Pulses
Pulse−by−Pulse Shutdown
Dual Source/Sink Outputs: "400 mA Peak
Pb−Free Packages are Available*
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16
1
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MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
SG3525AN
AWLYYWW
1
16
16
SOIC−16L
DW SUFFIX
CASE 751G
SG3525A
AWLYYWW
1
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN CONNECTIONS
Inv. Input 1
Noninv. Input 2
Sync 3
OSC. Output 4
CT 5
RT 6
Discharge 7
Soft−Start 8
16 Vref
15 VCC
14 Output B
13 VC
12 Ground
11 Output A
10 Shutdown
9 Compensation
(Top View)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
January, 2005 − Rev. 5
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
SG3525A/D




SG3525A pdf, 반도체, 판매, 대치품
SG3525A
ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 3], unless otherwise noted.)
Characteristics
Symbol Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (TJ = +25°C)
Line Regulation (+8.0 V VCC +35 V)
Load Regulation (0 mA IL 20 mA)
Temperature Stability
Total Output Variation Includes Line and Load Regulation over Temperature
Short Circuit Current (Vref = 0 V, TJ = +25°C)
Output Noise Voltage (10 Hz f 10 kHz, TJ = +25°C)
Long Term Stability (TJ = +125°C) (Note 4)
OSCILLATOR SECTION (Note 5, unless otherwise noted.)
Initial Accuracy (TJ = +25°C)
Frequency Stability with Voltage
(+8.0 V VCC +35 V)
Frequency Stability with Temperature
Minimum Frequency (RT = 150 kW, CT = 0.2 mF)
Maximum Frequency (RT = 2.0 kW, CT = 1.0 nF)
Current Mirror (IRT = 2.0 mA)
Clock Amplitude
Vref
Regline
Regload
DVref/DT
DVref
ISC
Vn
S
5.00
4.95
5.10
10
20
20
80
40
20
5.20
20
50
5.25
100
200
50
Vdc
mV
mV
mV
Vdc
mA
mVrms
mV/khr
Dfosc
DVCC
Dfosc
DT
fmin
fmax
±2.0 ±6.0
%
±1.0 ±2.0
%
±0.3 −
%
− 50 − Hz
400 −
− kHz
1.7 2.0 2.2 mA
3.0 3.5
V
Clock Width (TJ = +25°C)
Sync Threshold
0.3 0.5 1.0 ms
1.2 2.0 2.8
V
Sync Input Current (Sync Voltage = +3.5 V)
− 1.0 2.5 mA
ERROR AMPLIFIER SECTION (VCM = +5.1 V)
Input Offset Voltage
VIO − 2.0 10 mV
Input Bias Current
IIB − 1.0 10 mA
Input Offset Current
IIO − − 1.0 mA
DC Open Loop Gain (RL 10 MW)
AVOL 60 75 − dB
Low Level Output Voltage
VOL − 0.2 0.5 V
High Level Output Voltage
VOH
3.8 5.6
V
Common Mode Rejection Ratio (+1.5 V VCM +5.2 V)
CMRR
60
75
dB
Power Supply Rejection Ratio (+8.0 V VCC +35 V)
PSRR 50 60 − dB
PWM COMPARATOR SECTION
Minimum Duty Cycle
DCmin
0
%
Maximum Duty Cycle
DCmax 45 49 − %
Input Threshold, Zero Duty Cycle (Note 5)
Vth
0.6 0.9
V
Input Threshold, Maximum Duty Cycle (Note 5)
Vth − 3.3 3.6 V
Input Bias Current
IIB − 0.05 1.0 mA
3. Tlow = 0°
Thigh = +70°C
4. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average
stability from lot to lot.
5. Tested at fosc = 40 kHz (RT = 3.6 kW, CT = 0.01 mF, RD = 0 W).
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SG3525A 전자부품, 판매, 대치품
SG3525A
VCC
Q5
Q7
Q4
Vref
Q8
Q6
13
VC
Q9
Q10
5.0k
11, 14
Q11 Output
2.0k
Q1 Q2 Q3 Q6 Omitted
in SG3527A
5.0k 10k 10k
Clock F/F
PWM
Figure 9. Output Circuit
(1/2 Circuit Shown)
+Vsupply
Q1
To Output Filter
R1
R2
13
VC 11
A
SG3525A 14
B
GND
12
+Vsupply
R1
13
VC A 11
SG3525A
14
B
GND
12
C1
R2
C2
R3
Q1
Q2
T1
For single−ended supplies, the driver outputs are grounded.
The VC terminal is switched to ground by the totem−pole
source transistors on alternate oscillator cycles.
Figure 10. Single−Ended Supply
In conventional push−pull bipolar designs, forward base drive is
controlled by R1−R3. Rapid turn−off times for the power devices
are achieved with speed−up capacitors C1 and C2.
Figure 11. Push−Pull Configuration
+Vsupply
R1
13 11 Q1
VC A
SG3525A
14
GND B
12
Q2
T1
+Vsupply
13
11
VC A
SG3525A
14
GND B
12
T1
Q1
R1
Q2
R2
C1
T2
C2
The low source impedance of the output drivers provides
rapid charging of power FET input capacitance while
minimizing external components.
Figure 12. Driving Power FETS
Low power transformers can be driven directly by the SG3525A.
Automatic reset occurs during deadtime, when both ends of the
primary winding are switched to ground.
Figure 13. Driving Transformers in a
Half−Bridge Configuration
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