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SG3525A 데이터시트 PDF




STMicroelectronics에서 제조한 전자 부품 SG3525A은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 SG3525A 기능
기능 REGULATING PULSE WIDTH MODULATORS
제조업체 STMicroelectronics
로고 STMicroelectronics 로고


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SG3525A 데이터시트, 핀배열, 회로
SG2525A
® SG3525A
REGULATING PULSE WIDTH MODULATORS
. 8 TO 35 V OPERATION
. 5.1 V REFERENCE TRIMMED TO ± 1 %
. 100 Hz TO 500 KHz OSCILLATOR RANGE
. SEPARATE OSCILLATOR SYNC TERMINAL
. ADJUSTABLE DEADTIME CONTROL
. INTERNAL SOFT-START
. PULSE-BY-PULSE SHUTDOWN
. INPUT UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
. LATCHING PWM TO PREVENT MULTIPLE
PULSES
. DUAL SOURCE/SINK OUTPUT DRIVERS
DIP16
16(Narrow)
DESCRIPTION
The SG3525Aseries of pulse width modulator inte-
grated circuits are designed to offer improved per-
formance and lowered external parts count when
used in designing all types of switching power sup-
plies. The on-chip + 5.1 V reference is trimmed to ±
1 % and the input common-mode range of the error
amplifier includes the reference voltage eliminating
external resistors. A sync input to the oscillator al-
lows multiple units to be slaved or a single unit to be
synchronized to an external system clock. A single
resistor betweenthe CT andthe dischargeterminals
provide a wide range of dead time ad- justment.
Thesedevicesalso featurebuilt-insoft-startcircuitry
with only an external timing capacitor required. A
shutdownterminal controls both the soft-start circu-
ity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shut-
down, as well as soft-start recycle with longer shut-
down commands. These functions are also control-
led by an undervoltagelockoutwhich keepsthe out-
puts off and the soft-start capacitor discharged for
sub-normal input voltages. This lockout circuitry in-
cludesapproximately 500 mV of hysteresisfor jitter-
free operation. Another feature of these PWM cir-
cuits is a latch following the comparator. Once a
PWM pulses has been terminated for any reason,
the outputs will remain off for the duration of the pe-
riod. The latch is reset with each clock pulse. The
output stages are totem-pole designs capable of
sourcing or sinking in excess of 200 mA. The
SG3525Aoutputstage features NOR logic, giving a
LOW output for an OFF state.
PIN CONNECTIONS AND ORDERING NUMBERS (top view)
Type
SG2525A
SG3525A
Plastic DIP
SG2525AN
SG3525AN
SO16
SG2525AP
SG3525AP
June 2000
1/12




SG3525A pdf, 반도체, 판매, 대치품
SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Conditions
PWM COMPARATOR
Minimum Duty-cycle
Maximum Duty-cycle
Input Threshold
Zero Duty-cycle
Maximum Duty-cycle
* Input Bias Current
SHUTDOWN SECTION
Soft Start Current
VSD = 0 V, VSS = 0 V
Soft Start Low Level VSD = 2.5 V
Shutdown Threshold
To outputs, VSS = 5.1 V
Tj = 25 °C
Shutdown Input Current VSD = 2.5 V
* Shutdown Delay
VSD = 2.5 V Tj = 25 °C
OUTPUT DRIVERS (each output) (VC = 20 V)
Output Low Level
Isink = 20 mA
Output High Level
Isink = 100 mA
Isource = 20 mA
Under-Voltage Lockout
IC Collector Leakage
tr* Rise Time
tf* Fall Time
TOTAL STANDBY CURRENT
Isource = 100 mA
Vcomp and Vss = High
VC = 35 V
CL = 1 nF, Tj = 25 °C
CL = 1 nF, Tj = 25 °C
Is Supply Current
Vi = 35 V
SG2525A
Min. Typ. Max.
0
45 49
0.7 0.9
3.3 3.6
0.05 1
25 50 80
0.4 0.7
0.6 0.8 1
0.4 1
0.2 0.5
0.2 0.4
12
18 19
17 18
678
200
100 600
50 300
14 20
SG3525A
Min. Typ. Max.
0
45 49
0.7 0.9
3.3 3.6
0.05 1
25 50 80
0.4 0.7
0.6 0.8 1
0.4 1
0.2 0.5
0.2 0.4
12
18 19
17 18
678
200
100 600
50 300
14 20
Unit
%
%
V
V
µA
µA
V
V
mA
µs
V
V
V
V
V
µA
ns
ns
mA
* These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production.
Tested at fosc = 40 KHz (RT = 3.6 K, CT = 10nF, RD = 0 ). Approximate oscillator frequency is defined by :
f= 1
CT (0.7 RT + 3 RD)
.DC transconductance (gM) relates to DC open-loop voltage gain (Gv) according to the following equation : Gv = gM RL whereRL is the resistance
from pin 9 to ground. The minimum gM specification is used to calculate minimum Gv when the error amplifier output is loaded.
4/12

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SG3525A 전자부품, 판매, 대치품
Figure 5 : Error Amplifier.
SG2525A-SG3525A
PRINCIPLES OF OPERATION
SHUTDOWN OPTIONS (see Block Diagram)
Since both the compensation and soft-start termi-
nals (Pins 9 and 8) have current source pull-ups,
either can readily accept a pull-down signal which
only has to sink a maximum of 100 µA to turn off the
outputs.This is subject to the added requirement of
discharging whatever external capacitance may be
attached to these pins.
An alternateapproachis the useof the shutdowncir-
cuitry of Pin 10 which has been improved to en-
hance the available shutdown options. Activating
this circuit by applying a positive signal on Pin 10
performs two functions : the PWM latch is immedi-
ately set providing the fastest turn-off signal to the
outputs ; and a 150 µA current sink begins to dis-
charge the external soft-start capacitor. If the shut-
down command is short, the PWM signal is termi-
nated without significant discharge of the soft-start
capacitor, thus, allowing, for example, a convenient
implementation of pulse-by-pulse current limiting.
Holding Pin 10 high for a longer duration, however,
will ultimately discharge this external capacitor, re-
cycling slow turn-on upon release.
Pin 10 should not be left floating as noise pickup
could conceivably interrupt normal operation.
7/12

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