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PDF SI3211-KT Data sheet ( Hoja de datos )

Número de pieza SI3211-KT
Descripción PROSLIC PROGRAMMABLE CMOS SLIC/CODEC WITH RINGING/BATTERY VOLTAGE GENERATION
Fabricantes ETC 
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Si3210/Si3211/Si3212
PROSLIC™ PROGRAMMABLE CMOS SLIC/CODEC
WIT H RI NG ING /BAT TERY VOLTAGE GENERATIO N
Features
Performs all BORSCHT Functions
Ideal for Short Loop Applications
(5 REN at 2 kft, 3 REN at 4 kft)
Low Voltage CMOS
Package: 38-Pin TSSOP
Compliant with Relevant LSSGR and
CCITT Specifications
Battery Voltage Generated Dynamically
with On-Chip DC-DC Converter
Controller (Si3210 only)
5 REN Ringing Generator
Programmable Frequency, Amplitude,
Waveshape, and Cadence
Programmable AC Impedance
A-Law/µ-Law, Linear PCM Companding
On-Hook Transmission
Applications
Programmable Constant Current
Feed (20–41 mA)
Programmable Loop Closure and
Ring Trip Thresholds with Debouncing
Loop or Ground Start Operation and
Polarity Battery Reversal
Continuous Line Voltage and Current
Monitoring
DTMF Decoder
Dual Tone Generator
SPI and PCM Bus Digital Interfaces
with Programmable Interrupt for
Control and Data
3.3 V or 5 V Operation
Multiple Loopback Modes for Testing
Pulse Metering
FSK Caller ID Generation
Terminal Adaptors
Cable Telephony
PBX/Key Systems
Description
Wireless Local Loop
Voice Over IP
Integrated Access Devices
The ProSLIC™ is a low-voltage CMOS device that integrates SLIC, codec, and
battery generation functionality into a complete analog telephone interface. The
device is ideal for short loop applications such as terminal adaptors, cable telephony,
and wireless local loop. The ProSLIC is powered with a single 3.3 V or 5 V supply.
The Si3210 generates battery voltages dynamically using a software programmable
dc-dc converter from a 3.3 V to 35 V supply; negative high-voltage supplies are not
needed. All high voltage functions are performed locally with a few low cost discrete
components. The device is available in a 38-pin TSSOP and interfaces directly to
standard SPI and PCM bus digital interfaces.
Functional Block Diagram
Ordering Information
See page 118.
Pin Assignments
Si3210/11/12
CS
INT
PCLK
DRX
DTX
FSYNC
RESET
SDCH/DIO1
SDCL/DIO2
VDDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
STIPE
SVBAT
SRINGE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38 SCLK
37 SDI
36 SDO
35 SDITHRU
34 DCDRV/DCSW
33 DCFF/DOUT
32 TEST
31 GNDD
30 VDDD
29 ITIPN
28 ITIPP
27 VDDA2
26 IRINGP
25 IRINGN
24 IGMP
23 GNDA
22 IGMN
21 SRINGAC
20 STIPAC
INT RESET
CS
SCLK
SDO
SDI
DTX
Control
Interface
DRX
PCM
Interface
FSYNC
PCLK
PLL
Si3210/11/12
DTMF
Decode
Line
Status
Gain/
A tte n u a t i o n /
F il te r
Tone
G ene rator
A/D
Program
Hybrid
Line
Feed
Control
Gain/
A tte n u a ti o n /
F i l te r
D/A ZS
DC-D C Converter Controller
(Si3210 only)
TIP
Low Cost
E xtern al
Discretes
RING
Patents pending
Preliminary Rev. 1.11 9/01
Copyright © 2001 by Silicon Laboratories
Si3210-DS111
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

1 page




SI3211-KT pdf
Si3210/Si3211/Si3212
Table 3. AC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70°C for K-Grade, –40 to 85°C for B-Grade)
Parameter
Test Condition
Min
TX/RX Performance
Overload Level
Single Frequency Distortion1
Signal-to-(Noise + Distortion) Ratio2
THD = 1.5%
2-wire – PCM or
PCM – 2-wire:
200 Hz–3.4 kHz
200 Hz to 3.4 kHz
D/A or A/D 8-bit
Active off-hook, and OHT,
any ZAC
2.5
Figure 1
Audio Tone Generator
Signal-to-Distortion Ratio2
0 dBm0, Active off-hook,
and OHT, any Zac
45
Intermodulation Distortion
Gain Accuracy2
2-wire to PCM, 1014 Hz
–0.5
PCM to 2-wire, 1014 Hz
–0.5
Gain Accuracy Over Frequency
Figure 3,4
Group Delay Over Frequency
Gain Tracking3
1014 Hz sine wave, refer-
ence level –10 dBm
signal level:
Figure 5,6
3 dB to –37 dB
–0.25
–37 dB to –50 dB
–0.5
–50 dB to –60 dB
–1.0
Round-Trip Group Delay
at 1000 Hz
Gain Step Accuracy
–6 dB to 6 dB
–0.017
Gain Variation with Temperature
All gain settings
–0.25
Gain Variation with Supply
2-Wire Return Loss
VDDA = VDDA = 3.3/5 V ± 5%
200 Hz to 3.4 kHz
–0.1
30
Transhybrid Balance
300 Hz to 3.4 kHz
30
Idle Channel Noise4
Noise Performance
C-Message Weighted
Psophometric Weighted
3 kHz flat
PSRR from VDDA
RX and TX, DC to 3.4 kHz
40
PSRR from VDDD
RX and TX, DC to 3.4 kHz
40
PSRR from VBAT
RX and TX, DC to 3.4 kHz
40
Typ
0
0
1100
35
Max
Unit
— VPK
–45 dB
— dB
–41 dB
0.5 dB
0.5 dB
0.25
0.5
1.0
0.017
0.25
0.1
dB
dB
dB
µs
dB
dB
dB
dB
dB
15 dBrnC
–75 dBmP
18 dBrn
— dB
— dB
— dB
Preliminary Rev. 1.11
5

5 Page





SI3211-KT arduino
Si3210/Si3211/Si3212
Table 4. Linefeed Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70°C for K-Grade, –40 to 85°C for B-Grade)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Loop Resistance Range
RLOOP
See note.*
0 — 160
DC Loop Current Accuracy
ILIM = 29 mA, ETBA = 4 mA
–10
10
DC Open Circuit Voltage
Accuracy
Active Mode; VOC = 48 V, –4 —
VTIP – VRING
4
DC Differential Output
Resistance
RDO
ILOOP < ILIM
— 160 —
%
V
DC Open Circuit Voltage—
Ground Start
VOCTO
IRING<ILIM; VRING wrt ground
VOC = 48 V
–4
4
DC Output Resistance—
Ground Start
RROTO
IRING<ILIM; RING to ground
160
V
DC Output Resistance—
Ground Start
RTOTO
TIP to ground
150 — — k
Loop Closure/Ring Ground
Detect Threshold Accuracy
ITHR = 11.43 mA
–20 — 20 %
Ring Trip Threshold
Accuracy
RTHR = 1100
–20 — 20 %
Ring Trip Response Time
User Programmable Register 70 — — —
and Indirect Register 36
Ring Amplitude
Ring DC Offset
VTR 5 REN load; sine wave; 44 — — VRMS
RLOOP = 160 Ω, VBAT = –75 V
ROS Programmable in Indirect 0 — — V
Register 19
Trapezoidal Ring Crest
Factor Accuracy
Crest factor = 1.3
–.05 —
.05
Sinusoidal Ring Crest
Factor
RCF
1.35 — 1.45
Ringing Frequency Accuracy
Ringing Cadence Accuracy
Calibration Time
Power Alarm Threshold
Accuracy
f = 20 Hz
–1 — 1 %
Accuracy of ON/OFF Times –50
50 msec
CAL to CAL Bit
— — 600 msec
At Power Threshold = 300 mW –25
25
%
*Note: DC resistance round trip; 160 corresponds to 2 kft 26 gauge AWG.
Preliminary Rev. 1.11
11

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