PDF SAA7346H Data sheet ( Hoja de datos )

Número de pieza	SAA7346H
Descripción	Shock absorbing RAM addresser
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET SAA7346 Shock absorbing RAM addresser Preliminary speciﬁcation File under Integrated Circuits, IC01 July 1994 Philips Semiconductors 1 page Philips Semiconductors Shock absorbing RAM addresser SYMBOL D3 to D0 VSS2 VDD2 PIN 39 to 42 DRAM data bus inputs/outputs 43 supply ground 2 44 supply voltage 2 DESCRIPTION Preliminary speciﬁcation SAA7346 handbook, full pagewidth CFLG 1 KILL 2 SCLI 3 WCI 4 SDI 5 CONFIG 6 CLKIN 7 TMS 8 OTD 9 RCD2 10 SSD 11 SAA7346 33 A8 32 A0 31 A7 30 A1 29 A6 28 A2 27 A5 26 A3 25 A4 24 VSS1 23 VDD1 MGB430 Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION I2S input/output interfaces The SAA7346 contains an asynchronous serial input and a serial output interface. The serial operation of the interfaces is under hardware control of the external circuitry and uses the I2S protocol. The output presents a continuous clock signal SCLO (typically 2.8224 MHz) which is divided from the system clock, and a word select signal WCO, typically 44.1 kHz (fs), which is used to distinguish between right and left channels. When in by-pass mode WCO and SCLO are the same as the input interface signals WCI and SCLI, enabling data to pass through the SAA7346. Since the serial input port is asynchronous the device is independent of the CD decoder clock speed and enables the word clock to vary from 1.1 × fs to 4 × fs (typically 2 × fs). This is a requirement of any electronic shock absorbing system since the disc must be rotating faster than usual to assure the FIFO is full to absorb a shock. The falling edge of WCO indicates the start of a new transfer. Data is exchanged over the SDI and SDO pins. The SAA7346 is compatible with a variety of DAC ICs. New subcode frame regeneration The SAA7346 has a digital phase-locked loop (PLL) system which decodes the F1 and F6 flags, from the first 1-bit signal generated by the CD decoder correction flag output shown in Fig.3. The F1 flag is the absolute time sync signal of the New Subcode Frame (NSF). It relates July 1994 5 5 Page Philips Semiconductors Shock absorbing RAM addresser Preliminary speciﬁcation SAA7346 Table 6 SAA7346 I2S output speeds. RCD2 LOW LOW(2) LOW LOW HIGH HIGH I2S INPUT SPEED CAV(1) n=1 n=2 n=4 n=2 n=4 I2S OUTPUT SPEED n=1 n=1 n=1 n=1 n = 1⁄2 n = 1⁄2 APPLICATION CAV CDROM player with standard audio speed delay line feature shock proof CD player high data rate CDROM/CDI player with standard audio speed musicians feature musicians feature Notes 1. CAV with n = 4 speed at outer edge of disc; n = 1.5 at inner edge of disc. 2. To build-up a delay, RCD2 should be made HIGH temporarily for twice the delay time. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER VDD Pmax Tstg Tamb supply voltage maximum power dissipation storage temperature operating ambient temperature MIN. 0 − −55 −40 MAX. 6.5 500 +125 +85 UNIT V mW °C °C THERMAL CHARACTERISTICS SYMBOL PARAMETER Rth j-a thermal resistance from junction to ambient in free air VALUE 80 UNIT K/W CHARACTERISTICS VDD = 3.3 to 5.5 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS MIN. Supply VDD IDD IDDb supply voltage supply current bypass supply current IDDq quiescent supply current Digital inputs VDD = 5.0 V VDD = 5.0 V; bypass mode 3.3 − − − INPUTS: WCI, SDI, CLKIN, OTD AND RCD2; NORMAL CMOS VIL LOW level input voltage VIH HIGH level input voltage ILI input leakage current CI input capacitance VI = 0 V to VDD −0.3 0.7VDD −10 − July 1994 11 TYP. MAX. UNIT 5.0 5.5 12 − 4− − 100 V mA mA µA − 0.3VDD V − VDD + 0.3 V − +10 µA − 10 pF 11 Page

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