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부품번호 | SAB9083H 기능 |
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기능 | Multistandard Picture-In-Picture PIP controller | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 24 페이지수
INTEGRATED CIRCUITS
DATA SHEET
SAB9083
Multistandard Picture-In-Picture
(PIP) controller
Preliminary specification
Supersedes data of 1999 Feb 18
File under Integrated Circuits, IC02
1999 Nov 12
Philips Semiconductors
Multistandard Picture-In-Picture (PIP)
controller
Preliminary specification
SAB9083
PINNING
SYMBOL
Vref(B)(MA)
MU
VDDA(MF)
VSSA(MA)
VDDA(MA)
VDDA(DA)
VSSA(DA)
DY
Vbias(DA)
DV
Vref(T)(DA)
DU
Vref(B)(DA)
VDDD(DA)
VSSD(DA)
VSSD(P1)
VDDD(P1)
VSSD(T1)
VSSD(T2)
VDDD(RP)
n.c.
VSSD(T3)
n.c.
T5
T4
T3
T2
T1
T0
TC
VDDD(RL)
VSSD(RL)
VSSD(RM)
VDDD(RM)
TCLK
TM
TCBD
TCBC
TCBR
VSSD(T4) to VSSD(T7)
1999 Nov 12
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 to 29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 to 51
TYPE
DESCRIPTION
I/O analog bottom reference voltage for main channel ADCs
I analog U input for main channel
S analog supply voltage for main channel front-end buffers
S analog ground for main channel ADCs
S analog supply voltage for main channel ADCs
S analog supply voltage for DACs
S analog ground for DACs
O analog Y output of DAC
I/O input/output analog bias reference voltage for DACs
O analog V output of DAC
I/O input/output analog top reference voltage for DACs
O analog U output of DAC
I/O analog bottom reference voltage for DACs
S digital supply voltage for DACs
S digital ground for DACs
S digital ground for periphery
S digital supply voltage for periphery
S digital ground for test
S digital ground for test
S digital supply voltage for memory periphery
− not connected
S digital ground for test
− not connected
I/O test data input/output bit 5 (CMOS levels)
I/O test data input/output bit 4 (CMOS levels)
I/O test data input/output bit 3 (CMOS levels)
I/O test data input/output bit 2 (CMOS levels)
I/O test data input/output bit 1 (CMOS levels)
I/O test data input/output bit 0 (CMOS levels)
I test control input (CMOS levels)
S digital supply voltage for memory logic
S digital ground for memory logic
S digital ground for memory core
S digital supply voltage for memory core
I test clock input (CMOS levels)
I test mode input (CMOS levels)
I test control block data input (CMOS levels)
I test control block clock input (CMOS levels)
I test control block reset input (CMOS levels)
S digital ground for test
4
4페이지 Philips Semiconductors
Multistandard Picture-In-Picture (PIP)
controller
Preliminary specification
SAB9083
FUNCTIONAL DESCRIPTION
Acquisition
The internal pixel rate is 28 MHz for the Y, U and V
channels. It is expected that the bandwidth of the input
signals will be limited to 4.5 MHz for the Y input and
1.125 MHz for the U and V inputs. Inset synchronisation is
achieved via the acquisition HSYNC and VSYNC pins of
the main channel. The display is driven by the main
channel clock.
The starting-point of the acquisition can be controlled with
the acquisition fine positioning added to a system
constant. With a nominal input fHSYNC and standard NTSC
signals, 1408 samples (active video) are acquired and
processed by the SAB9083. Here, the nominal input
fHSYNC results in a nominal system clock frequency of
1792 × fHSYNC (approximately 28 MHz).
PIP modes
handbook, full pagewidth
MAIN
SUB
SUB
MAIN
MAIN
REPLAY
SUB
MGM810
Fig.3 PIP modes.
1999 Nov 12
7
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SAB9083 | Multistandard Picture-In-Picture PIP controller | NXP Semiconductors |
SAB9083H | Multistandard Picture-In-Picture PIP controller | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |