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M48Z19 데이터시트 PDF




STMicroelectronics에서 제조한 전자 부품 M48Z19은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 M48Z19 자료 제공

부품번호 M48Z19 기능
기능 CMOS 8K x 8 ZEROPOWER SRAM
제조업체 STMicroelectronics
로고 STMicroelectronics 로고


M48Z19 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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M48Z19 데이터시트, 핀배열, 회로
M48Z09
M48Z19
CMOS 8K x 8 ZEROPOWER SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
POWER-FAIL INTERRUPT
CHOICE of TWO WRITE PROTECT
VOLTAGES:
– M48Z09: 4.5V VPFD 4.75V
– M48Z19: 4.2V VPFD 4.5V
SELF CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
11 YEARS of DATA RETENTION in the
ABSENCE of POWER
PIN and FUNCTION COMPATIBLE with the
MK48Z09, 19 and JEDEC STANDARD 8K x 8
SRAMs
28
1
PCDIP28 (PC)
Battery CAPHAT
Figure 1. Logic Diagram
DESCRIPTION
The M48Z09,19 ZEROPOWER® RAM is an 8K x 8
non-volatile static RAM which is pin and function
compatible with the MK48Z09,19.
A special 28 pin 600mil DIP CAPHATpackage
houses the M48Z09,19 silicon with a long life lith-
ium button cell to form a highly integrated battery
backed-up memory solution.
Table 1. Signal Names
A0-A12
Address Inputs
DQ0-DQ7 Data Inputs / Outputs
INT Power Fail Interrupt
E1 Chip Enable 1
E2 Chip Enable 2
G Output Enable
W Write Enable
VCC Supply Voltage
VSS Ground
VCC
13
A0-A12
8
DQ0-DQ7
W
M48Z09
E1 M48Z19 INT
E2
G
VSS
AI01184
November 1994
1/13




M48Z19 pdf, 반도체, 판매, 대치품
M48Z09, M48Z19
Table 4. Capacitance (1) (TA = 25 °C)
Symbol
Parameter
Test Condition Min Max
CIN Input Capacitance
VIN = 0V
CIO (2)
Input / Output Capacitance
VOUT = 0V
Notes: 1. Effective capacitance calculated from the equation C = It/V with V = 3V and power supply at 5V.
2. Outputs deselected
10
10
Unit
pF
pF
Table 5. DC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
ILI
ILO
ICC
ICC1
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
ICC2 Supply Current (Standby) CMOS
VIL Input Low Voltage
VIH Input High Voltage
Output Low Voltage
VOL
Output Low Voltage (INT) (1)
VOH Output High Voltage
Note: 1. The INT pin is Open Drain.
Test Condition
0V VIN VCC
0V VOUT VCC
Outputs open
E1 = VIH, E2 = VIL
E1 = VCC – 0.2V,
E2 = VSS + 0.2V
IOL = 2.1mA
IOL = 0.5mA
IOH = –1mA
Min
–0.3
2.2
2.4
Max
±1
±5
80
3
3
0.8
VCC + 0.3
0.4
0.4
Unit
µA
µA
mA
mA
mA
V
V
V
V
V
Table 6. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70°C)
Symbol
Parameter
VPFD
Power-fail Deselect Voltage (M48Z09)
VPFD Power-fail Deselect Voltage (M48Z19)
VSO Battery Back-up Switchover Voltage
tDR Expected Data Retention Time
Note: 1. All voltages referenced to VSS.
Min Typ Max Unit
4.5 4.6 4.75 V
4.2 4.3 4.5
V
3.0 V
11 YEARS
4/13

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M48Z19 전자부품, 판매, 대치품
M48Z09, M48Z19
Table 9. Write Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
M48Z09 / 19
-100
Min Max
tAVAV
Write Cycle Time
100
tAVWL
Address Valid to Write Enable Low
0
tAVE1L
Address Valid to Chip Enable 1 Low
0
tAVE2H
Address Valid to Chip Enable 2 High
0
tWLWH
Write Enable Pulse Width
80
tE1LE1H
Chip Enable 1 Low to Chip Enable 1 High
80
tE2HE2L
Chip Enable 2 High to Chip Enable 2 Low
80
tWHAX
Write Enable High to Address Transition
10
tE1HAX
Chip Enable 1 High to Address Transition
10
tE2LAX
Chip Enable 2 Low to Address Transition
10
tDVWH
Input Valid to Write Enable High
50
tDVE1H
Input Valid to Chip Enable 1 High
50
tDVE2L
Input Valid to Chip Enable 2 Low
50
tWHDX
Write Enable High to Input Transition
5
tE1HDX
Chip Enable 1 High to Input Transition
5
tE2LDX
tWLQZ (1, 2)
Chip Enable 2 Low to Input Transition
Write Enable Low to Output Hi-Z
5
50
tAVWH
Address Valid to Write Enable High
80
tAVE1H
Address Valid to Chip Enable 1 High
80
tAVE2L
Address Valid to Chip Enable 2 Low
80
tWHQX (1, 2)
Write Enable High to Output Transition
10
Notes: 1. CL= 30pF (see Figure 4).
2. If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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