|
|
PDF DS92LV1260TUJB Data sheet ( Hoja de datos )
| Número de pieza | DS92LV1260TUJB | |
| Descripción | Six Channel 10 Bit BLVDS Deserializer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS92LV1260TUJB (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
August 2003
DS92LV1260
Six Channel 10 Bit BLVDS Deserializer
General Description
The DS92LV1260 integrates six deserializer devices into a
single chip. The chip uses a 0.25u CMOS process technol-
ogy. The DS92LV1260 can simultaneously deserialize up to
six data streams that have been serialized by the National
Semiconductor DS92LV1021 or DS92LV1023 Bus LVDS se-
rializers. The device also includes a seventh serial input
channel that serves as a redundant input.
Each deserializer block in the DS92LV1260 operates inde-
pendently with its own clock recovery circuitry and lock-
detect signaling.
The DS92LV1260 uses a single +3.3V power supply with a
typical power dissipation of 1.2W at 3.3V with a PRBS-15
pattern. Refer to the Connection Diagrams for packaging
information.
Features
n Deserializes one to six BusLVDS input serial data
streams with embedded clocks
n Seven selectable serial inputs to support n+1
redundancy of deserialized streams
n Seventh channel has single pin monitor output that
reflects input from seventh channel input
n Parallel clock rate up to 40MHz
n On chip filtering for PLL
n Absolute maximum worst case power dissipation =
1.9W at 3.6V
n High impedance inputs upon power off (Vcc = 0V)
n Single power supply at +3.3V
n 196-pin LBGA package (Low-profile Ball Grid Array)
package
n Industrial temperature range operation: −40˚C to +85˚C
Block Diagram
Application
© 2003 National Semiconductor Corporation DS200002
20000202
www.national.com
1 page  
AC Timing Diagrams and Test Circuits (Continued)
FIGURE 4. Locktime to SYNCPAT tDSR2
20000211
FIGURE 5. Unlock
20000213
20000231
FIGURE 6. Deserializer Data Valid Out Times
5
www.national.com
5 Page 
Application Information (Continued)
• Use at least 4 PCB board layers (Bus LVDS signals,
ground, power, and TTL signals).
Power system performance may be greatly improved by
using thin dielectrics (4 to 10 mils) for power/ground
sandwiches. This increases the intrinsic capacitance of
the PCB power system which improves power supply
filtering, especially at high frequencies, and makes the
value and placement of external bypass capacitors less
critical.
• Keep Serializers and Deserializers as close to the (Bus
LVDS port side) connector as possible.
Longer stubs lower the impedance of the bus, increase
the load on the Serializer, and lower the threshold margin
at the Deserializers. Deserializer devices should be
placed much less than one inch from slot connectors.
Because transition times are very fast on the Serializer
Bus LVDS outputs, reducing stub lengths as much as
possible is the best method to ensure signal integrity.
• Bypass each Bus LVDS device and also use distributed
bulk capacitance between power planes.
Surface mount capacitors placed close to power and
ground pins work best. External bypass capacitors
should include both RF ceramic and tantalum electrolytic
types. RF capacitors may use values in the range 0.001
µF to 0.1 µF. Tantalum capacitors may be in the range 2.2
µF to 10 µF. Voltage rating for tantalum capacitors should
be at least 5X the power supply voltage being used.
Randomly distributed by-pass capacitors should also be
used.
Package and pin layout permitting, it is also recom-
mended to use two vias at each power pin as well as all
RF bypass capacitor terminals. Dual vias reduce the
interconnect inductance between layers by up to half,
thereby reducing interconnect inductance and extending
the effective frequency range of the bypass components.
The outer layers of the PCB may be flooded with addi-
tional ground planes. These planes will improve shielding
and isolation as well as increase the intrinsic capacitance
of the power supply plane system. Naturally, to be effec-
tive, these planes must be tied to the ground supply
plane at frequent intervals with vias. Frequent via place-
ment improves signal integrity on signal transmission
lines by providing short paths for image currents, which
reduces signal distortion. Depending on which is greater,
the planes should be pulled back from all transmission
lines and component mounting pads a distance equal to
the width of the widest transmission line or the thickness
of the dielectric separating the transmission line from the
internal power or ground plane(s). Doing so minimizes
effects on transmission line impedances and reduces
unwanted parasitic capacitances at component mounting
pads.
• Use a termination resistor which best matches the differ-
ential impedance of your transmission line.
• Leave unused Bus LVDS receiver inputs open (floating).
Limit traces on unused inputs to <0.5 inches.
• Isolate TTL signals from Bus LVDS signals.
• Use controlled impedance media.
The backplane and connectors should have a matched
differential impedance.
For a typical application circuit, please see Figure 8.
There are more common practices which should be followed
when designing PCBs for LVDS signaling. General applica-
tion guidelines and hints may be found in the following
application notes: AN-808, AN-903, AN-971, AN-977, and
AN-1108. For packaging information on BGA’s, please see
AN-1126.
USING TDJIT AND TRNM TO VALIDATE SIGNAL
QUALITY
The parameter tRNM is calculated by first measuring how
much of the ideal bit the receiver needs to ensure correct
sampling. After determining this amount, what remains of the
ideal bit that is available for external sources of noise is
called tRNM.
The vertical limits of the mask are determined by the
DS92LV1260 receiver input threshold of +/− 50mV.
Please refer to the eye mask pattern of Figure 10 for a
graphic representation of tDJIT and tRNM.
11 www.national.com
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet DS92LV1260TUJB.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS92LV1260TUJB | Six Channel 10 Bit BLVDS Deserializer | National Semiconductor |
| DS92LV1260TUJB | Six Channel 10 Bit BLVDS Deserializer | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |