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부품번호 | XCV300E-8BG240I 기능 |
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기능 | Virtex-E 1.8 V Field Programmable Gate Arrays | ||
제조업체 | Xilinx | ||
로고 | |||
전체 5 페이지수
0
R Virtex™-E 1.8 V
Field Programmable Gate Arrays
DS022-1 (v2.2) November 9, 2001
00
Features
• Fast, High-Density 1.8 V FPGA Family
- Densities from 58 k to 4 M system gates
- 130 MHz internal performance (four LUT levels)
- Designed for low-power operation
- PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
• Highly Flexible SelectI/O+™ Technology
- Supports 20 high-performance interface standards
- Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
• Differential Signalling Support
- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
- Differential I/O signals can be input, output, or I/O
- Compatible with standard differential devices
- LVPECL and LVDS clock inputs for 300+ MHz
clocks
• Proprietary High-Performance SelectLink™
Technology
- Double Data Rate (DDR) to Virtex-E link
- Web-based HDL generation methodology
• Sophisticated SelectRAM+™ Memory Hierarchy
- 1 Mb of internal configurable distributed RAM
- Up to 832 Kb of synchronous internal block RAM
- True Dual-Port™ BlockRAM capability
- Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
- Designed for high-performance Interfaces to
External Memories
- 200 MHz ZBT* SRAMs
- 200 Mb/s DDR SDRAMs
- Supported by free Synthesizable reference design
* ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary Product Specification
• High-Performance Built-In Clock Management Circuitry
- Eight fully digital Delay-Locked Loops (DLLs)
- Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
- Clock Multiply and Divide
- Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
• Flexible Architecture Balances Speed and Density
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input function
- Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
- Internal 3-state bussing
- IEEE 1149.1 boundary-scan logic
- Die-temperature sensor diode
• Supported by Xilinx Foundation™ and Alliance Series™
Development Systems
- Further compile time reduction of 50%
- Internet Team Design (ITD) tool ideal for
million-plus gate density designs
- Wide selection of PC and workstation platforms
• SRAM-Based In-System Configuration
- Unlimited re-programmability
• Advanced Packaging Options
- 0.8 mm Chip-scale
- 1.0 mm BGA
- 1.27 mm BGA
- HQ/PQ
m• 0.18 m 6-Layer Metal Process
• 100% Factory Tested
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Ordering Information
Example: XCV300E-6PQ240C
Device Type
Speed Grade
(-6, -7, -8)
Temperature Range
C = Commercial (Tj = 0 C to +85 C)
I = Industrial (Tj = -40 C to +100 C)
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
HQ = High Heat Dissipation
Figure 1: Ordering Information
DS022_043_072000
R
Revision History
The following table shows the revision history for this document.
Date
12/7/99
1/10/00
1/28/00
2/29/00
5/23/00
7/10/00
8/1/00
9/20/00
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Revision
Initial Xilinx release.
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, TBYP values, buffered Hex Line info, p. 8, I/O Timing
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
Updated pinout tables, VCC page 20, and corrected Figure 20.
Correction to table on p. 22.
• Numerous minor edits.
• Data sheet upgraded to Preliminary.
• Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
• Reformatted entire document to follow new style guidelines.
• Changed speed grade values in tables on pages 35-37.
• Min values added to Virtex-E Electrical Characteristics tables.
• XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
• Corrected user I/O count for XCV100E device in Table 1 (Module 1).
• Changed several pins to “No Connect in the XCV100E“ and removed duplicate VCCINT
pins in Table ~ (Module 4).
• Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
• Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4).
• Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
Module 1 of 4
4
www.xilinx.com
1-800-255-7778
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
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XCV300E-8BG240C | Virtex-E 1.8 V Field Programmable Gate Arrays | Xilinx |
XCV300E-8BG240I | Virtex-E 1.8 V Field Programmable Gate Arrays | Xilinx |
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