XCV400E-8FG240I Datasheet PDF - Xilinx
| Part Number | XCV400E-8FG240I | |
| Description | Virtex-E 1.8 V Field Programmable Gate Arrays | |
| Manufacturers | Xilinx | |
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R Virtex™-E 1.8 V
Field Programmable Gate Arrays
DS022-1 (v2.2) November 9, 2001
00
Features
• Fast, High-Density 1.8 V FPGA Family
- Densities from 58 k to 4 M system gates
- 130 MHz internal performance (four LUT levels)
- Designed for low-power operation
- PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
• Highly Flexible SelectI/O+™ Technology
- Supports 20 high-performance interface standards
- Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
• Differential Signalling Support
- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
- Differential I/O signals can be input, output, or I/O
- Compatible with standard differential devices
- LVPECL and LVDS clock inputs for 300+ MHz
clocks
• Proprietary High-Performance SelectLink™
Technology
- Double Data Rate (DDR) to Virtex-E link
- Web-based HDL generation methodology
• Sophisticated SelectRAM+™ Memory Hierarchy
- 1 Mb of internal configurable distributed RAM
- Up to 832 Kb of synchronous internal block RAM
- True Dual-Port™ BlockRAM capability
- Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
- Designed for high-performance Interfaces to
External Memories
- 200 MHz ZBT* SRAMs
- 200 Mb/s DDR SDRAMs
- Supported by free Synthesizable reference design
* ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary Product Specification
• High-Performance Built-In Clock Management Circuitry
- Eight fully digital Delay-Locked Loops (DLLs)
- Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
- Clock Multiply and Divide
- Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
• Flexible Architecture Balances Speed and Density
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input function
- Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
- Internal 3-state bussing
- IEEE 1149.1 boundary-scan logic
- Die-temperature sensor diode
• Supported by Xilinx Foundation™ and Alliance Series™
Development Systems
- Further compile time reduction of 50%
- Internet Team Design (ITD) tool ideal for
million-plus gate density designs
- Wide selection of PC and workstation platforms
• SRAM-Based In-System Configuration
- Unlimited re-programmability
• Advanced Packaging Options
- 0.8 mm Chip-scale
- 1.0 mm BGA
- 1.27 mm BGA
- HQ/PQ
m• 0.18 m 6-Layer Metal Process
• 100% Factory Tested
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
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R Virtex™-E 1.8 V Field Programmable Gate Arrays
Date
11/20/00
2/12/01
4/2/01
10/25/01
11/09/01
Version
1.8
1.9
2.0
2.1
2.2
Revision
• Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.
• Updated minimums in Table 13 and added notes to Table 14.
• Added to note 2 to Absolute Maximum Ratings.
• Changed speed grade -8 numbers for TSHCKO32, TREG, TBCCS, and TICKOF.
• Changed all minimum hold times to –0.4 under Global Clock Setup and Hold for
LVTTL Standard, with DLL.
• Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters.
• Changed GCLK0 to BA22 for FG860 package in Table 46.
• Revised footnote for Table 14.
• Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.
• Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
• Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.
• Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
• Updated numerous values in Virtex-E Switching Characteristics tables.
• Converted data sheet to modularized format. See the Virtex-E Data Sheet section.
• Updated the Virtex-E Device/Package Combinations and Maximum I/O table to
show XCV3200E in the FG1156 package.
• Minor edits.
Virtex-E Data Sheet
The Virtex-E Data Sheet contains the following modules:
• DS022-1, Virtex-E 1.8V FPGAs:
Introduction and Ordering Information (Module 1)
• DS022-2, Virtex-E 1.8V FPGAs:
Functional Description (Module 2)
• DS022-3, Virtex-E 1.8V FPGAs:
DC and Switching Characteristics (Module 3)
• DS022-4, Virtex-E 1.8V FPGAs:
Pinout Tables (Module 4)
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
5
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| XCV400E-8FG240I | The function is Virtex-E 1.8 V Field Programmable Gate Arrays. Xilinx | |
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