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부품번호 XR16C2850IP40 기능
기능 3.3V AND 5V DUART WITH 128-BYTE FIFO
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XR16C2850IP40 데이터시트, 핀배열, 회로
áç
XR16C2850
APRIL 2002
3.3V AND 5V DUART WITH 128-BYTE FIFO
REV. 2.0.0
GENERAL DESCRIPTION
The XR16C28501 (2850) is an enhanced dual univer-
sal asynchronous receiver and transmitter (UART).
Enhanced features include 128 bytes of TX and RX
FIFOs, programmable TX and RX FIFO trigger level,
FIFO level counters, automatic (RTS/CTS) hardware
and (Xon/Xoff) software flow control, automatic RS-
485 half duplex direction control output and data rates
up to 6.25 Mbps at 5V and 8X sampling clock. On-
board status registers provide the user with opera-
tional status and data error flags. An internal loop-
back capability allows system diagnostics. The 2850
has a full modem interface and can operate at 3.3 V
or 5 V and is pin-to-pin compatible to Exar’s
ST16C2550 and XR16C2750 except the 48-TQFP
package. The 2850 register set is compatible to the
industry standard ST16C2550 and is available in 48-
pin TQFP, 44-pin PLCC and 40-pin PDIP packages.
The 40-pin package does not offer TXRDY# and
RXRDY# pins (DMA signal monitoring) otherwise the
three package versions are the same.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,832,205
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FEATURES
Pin-to-pin compatible and functionally compatible to
Exar’s ST16C2550 and XR16L2750 and TI’s
TL16C752B on the 44-PLCC package
Pin-alike Exar’s XR16L2750 and ST16C2550 48-
TQFP package but with additional CLK8/16, CLK-
SEL and HDCNTL inputs
Two independent UART channels
Register set compatible to 16C550
Up to 6.25 Mbps at 5V, and 4 Mbps at 3.3V
Transmit and Receive FIFOs of 128 bytes
Programmable TX and RX FIFO Trigger Levels
Transmit and Receive FIFO Level Counters
Automatic Hardware (RTS/CTS) Flow Control
Selectable Auto RTS Flow Control Hysteresis
Automatic Software (Xon/Xoff) Flow Control
Automatic RS-485 Half-duplex Direction Control
Output
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode
Full modem interface
Device Identification and Revision
Crystal oscillator or external clock input
Industrial and commercial temperature ranges
48-TQFP and 44-PLCC packages
FIGURE 1. XR16C2850 BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
HDCNTL#
CLKSEL
CLK8/16
Reset
8-bit Data
Bus
Interface
UART Channel A
UART
Regs
BRG
128 Byte TX FIFO
TX & RX
IR
ENDEC
128 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
3.3V or 5V VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
EXAR Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com [email protected]




XR16C2850IP40 pdf, 반도체, 판매, 대치품
áç
3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850
REV. 2.0.0
NAME
RXA
RXB
40-PDIP
PIN #
10
9
44-PLCC
PIN #
11
10
RTSA#
RTSB#
32
24
CTSA#
CTSB#
36
25
DTRA#
DTRB#
DSRA#
DSRB#
33
34
37
22
CDA#
CDB#
38
19
RIA#
RIB#
39
23
OP2A#
OP2B#
31
13
36
27
40
28
37
38
41
25
42
21
43
26
35
15
ANCILLARY SIGNALS
XTAL1
16
XTAL2
17
HDCNTL#
-
18
19
-
48-TQFP
PIN #
5
4
33
22
38
23
34
35
39
20
40
16
41
21
32
9
13
14
37
TYPE
DESCRIPTION
I UART channel A Receive Data or infrared receive data.
Normal receive data input must idle at logic 1 condition.
The infrared receiver pulses typically idles at logic 0 but
can be inverted by software control prior going in to the
decoder, see MCR[6] and FCTR[2]. If this pin is not used,
tie it to VCC or pull it high via a 100k ohm resistor.
O UART channel A or B Request-to-Send (active low) or
general purpose output. This output must be asserted
prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6].
I UART channel A or B Clear-to-Send (active low) or gen-
eral purpose input. It can be used for auto CTS flow con-
trol, see EFR[7], and IER[7]. This input should be
connected to VCC when not used.
O UART channel A or B Data-Terminal-Ready (active low)
or general purpose output. If it is not used, leave it uncon-
nected.
I UART channel A or B Data-Set-Ready (active low) or
general purpose input. This input should be connected to
VCC when not used. This input has no effect on the
UART.
I UART channel A or B Carrier-Detect (active low) or gen-
eral purpose input. This input should be connected to
VCC when not used. This input has no effect on the
UART.
I UART channel A or B Ring-Indicator (active low) or gen-
eral purpose input. This input should be connected to
VCC when not used. This input has no effect on the
UART.
O Output Port 2 channel A or B - The output state is defined
by the user and through the software setting of MCR[3].
INTA or INTB is set to the active mode and OP2A# or
OP2B# output to a logic 0 when MCR[3] is set to a logic
1. INTA or INTB is set to the three state mode and OP2A#
or OP2B# to a logic 1 when MCR[3] is set to a logic 0.
See MCR[3]. This output should not be used as a general
output else it will disturb the INTA or INTB output function-
ality.
I Crystal or external clock input.
O Crystal or buffered clock output.
I RS-485 half duplex directional control for channel A and B
(active low). Connect to VCC for normal RTS# function
and connect to GND for RS-485 half duplex direction con-
trol. RTS# pin goes low for transmit and high for receive.
This pin is wire “OR-ed” with FCTR[3]. See FCTR[3].
4

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XR16C2850IP40 전자부품, 판매, 대치품
XR16C2850
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
áç
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU INTERFACE
The CPU interface is 8 data bits wide with 3 address
lines and control signals to execute data bus read and
write transactions. The 2850 data interface supports
the Intel compatible types of CPUs and it is compati-
ble to the industry standard 16C550 UART. No clock
(oscillator nor external clock) is required to operate a
data bus transaction. Each bus cycle is asynchronous
using CS#, IOR# and IOW# signals. Both UART
channels share the same data bus for host opera-
tions. The data bus interconnections are shown in
Figure 3.
FIGURE 3. XR16C2850 DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_CSA#
UART_CSB#
UART_INTA
UART_INTB
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
UART_RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
VCC
UART
Channel A
TXA
RXA
DTRA#
RTSA#
CTSA#
DSRA#
CDA#
RIA#
OP2A#
CSA#
CSB#
INTA
INTB
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
UART
Channel B
TXB
RXB
DTRB#
RTSB#
CTSB#
DSRB#
CDB#
RIB#
OP2B#
RESET
GND
VCC
Serial Interfaceof
RS-232, RS-485
Serial Interface of RS-
232, RS-485
2750int
2.2 DEVICE RESET
The RESET input resets the internal registers and the
serial interface outputs in both channels to their de-
fault state (see Table 16 on page 30). An active high
pulse of longer than 40 ns duration will be required to
activate the reset function in the device.
2.3 DEVICE IDENTIFICATION AND REVISION
The XR16C2850 provides a Device Identification
code and a Device Revision code to distinguish the
part from other devices and revisions. To read the
identification code from the part, it is required to set
the baud rate generator registers DLL and DLM both
to 0x00. Now reading the content of the DLM will pro-
vide 0x12 for the XR16C2850 and reading the con-
tent of DLL will provide the revision of the part; for ex-
ample, a reading of 0x01 means revision A.
2.4 CHANNEL A AND B SELECTION
The UART provides the user with the capability to bi-
directionally transfer information between an external
CPU and an external serial communication device. A
logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure,
send transmit data and/or unload receive data to/from
the UART. Selecting both UARTs can be useful dur-
ing power up initialization to write to the same internal
registers, but do not attempt to read from both uarts
simultaneously. Individual channel select functions
are shown in Table 1.
TABLE 1: CHANNEL A AND B SELECT
CSA#
CSB#
FUNCTION
1 1 UART de-selected
0 1 Channel A selected
1 0 Channel B selected
0 0 Channel A and B selected
7

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XR16C2850IP40

3.3V AND 5V DUART WITH 128-BYTE FIFO

Exar Corporation
Exar Corporation

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