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기능 3.3V AND 5V DUART WITH 128-BYTE FIFO
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XR16C2852 데이터시트, 핀배열, 회로
áç
XR16C2852
APRIL 2002
3.3V AND 5V DUART WITH 128-BYTE FIFO
REV. 2.0.0
GENERAL DESCRIPTION
The XR16C28521 (2852) is a dual universal asyn-
chronous receiver and transmitter (UART). The de-
vice operates at 3.3V and 5V and is pin-to-pin com-
patible to Exar’s ST16C2552 and XR16L2752. The
2852 register set is compatible to the ST16C2552
and the XR16C2752 enhanced features. It supports
the Exar’s enhanced features of 128 bytes of TX and
RX FIFOs, programmable FIFO trigger level and
FIFO level counters, automatic hardware (RTS/CTS)
and software flow control, automatic RS-485 half du-
plex direction control output and a complete modem
interface. Onboard registers provide the user with op-
erational status and data error flags. An internal loop-
back capability allows system diagnotics. Indepen-
dent programmable baud rate generators are provid-
ed in each channel to select data rates up to 3.125
Mbps at 5V. The 2852 is available in the 44-pin PLCC
package.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,832,205
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FEATURES
Pin-to-pin compatible to Exar’s ST16C2552 and
XR16L2752
Improved version of PC16C552
Two independent UART channels
Register set compatible to 16C550
Up to 3 Mbps at 5V, and 2 Mbps at 3.3V
Transmit and Receive FIFOs of 128 bytes
Programmable TX and RX FIFO Trigger Levels
Transmit and Receive FIFO Level Counters
Automatic Hardware (RTS/CTS) Flow Control
Selectable Auto RTS Flow Control Hysteresis
Automatic Software (Xon/Xoff) Flow Control
Automatic RS-485 Half-duplex Direction Control
Output
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode
Full modem interface
Alternate Function Register
Device Identification and Revision
Crystal oscillator or external clock input
3.3 V or 5 V operation
Industrial and commercial temperature ranges
44-PLCC package
FIGURE 1. XR16C2852 BLOCK DIAGRAM
A 2 :A 0
D 7 :D 0
IO R #
IOW #
CS#
CHSEL
IN T A
IN T B
TXRDYA#
TXRDYB#
MFA#
(O P 2A #,
BAUDOUTA#, or
RXRDYA#)
MFB#
(O P 2B #,
BAUDOUTB#, or
RXRDYB#)
Reset
8-bit Data
Bus
In te r fa c e
UART Channel A
UART
Regs
BRG
128 Byte TX FIFO
TX & RX
IR
ENDEC
128 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
M odem Control Logic
3.3V or 5V VCC
GND
TXA (or TXIRA)
RXA (or RXIRA)
TXB (or TXIRB)
RXB (or RXIRB)
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
EXAR Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com [email protected]




XR16C2852 pdf, 반도체, 판매, 대치품
áç
3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2852
REV. 2.0.0
NAME
MFB#
44-PLCC
PIN #
19
TYPE
DESCRIPTION
O Multi-Function Output ChannelB. This output pin can function as the OP2B#, BAUD-
OUTB#, or RXRDYB# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is a logic 0 when MCR
bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after
a reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate clock
output is available at this pin.
TXA 38
TXB 26
RXA
RXB
39
25
RTSA#
RTSB#
36
23
CTSA#
CTSB#
40
28
DTRA#
DTRB#
DSRA#
DSRB#
37
27
41
29
CDA#
CDB#
42
30
RIA#
RIB#
43
31
ANCILLARY SIGNALS
XTAL1
11
XTAL2
13
RESET
21
VCC
44, 33
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data transfers.
See Table 2 on page 7 for more details.
O UART channel A or B Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a
logic 1 during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is a logic 0. If it is not used, leave it unconnected.
I UART channel A or B Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver pulses typically idles at logic
0 but can be inverted by software control prior going in to the decoder, see MCR[6]
and FCTR[2]. If this pin is not used, tie to VCC or pull it high via a 100k ohm resistor.
O UART channel A or B Request-to-Send (active low) or general purpose output. This
output must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6].
I UART channel A or B Clear-to-Send (active low) or general purpose input. It can be
used for auto CTS flow control, see EFR[7], and IER[7]. This input should be con-
nected to VCC when not used.
O UART channel A or B Data-Terminal-Ready (active low) or general purpose output. If
this pin is not used, leave it unconnected.
I UART channel A or B Data-Set-Ready (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on the
UART.
I UART channel A or B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I UART channel A or B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I Crystal or external clock input.
O Crystal or buffered clock output.
I Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will reset the internal
registers and all outputs. The UART transmitter output will be held at logic 1, the
receiver input will be ignored and outputs are reset during reset period (see External
Reset Conditions).
Pwr 3.3V or 5V power supply. Please note that the inputs are not 5V tolerant when oper-
ating at 3.3V.
4

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XR16C2852 전자부품, 판매, 대치품
XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
áç
TABLE 1: CHANNEL A AND B SELECT
CS# CHSEL
1X
01
00
FUNCTION
UART de-selected
Channel A selected
Channel B selected
2.5 CHANNEL A AND B INTERNAL REGISTERS
Each UART channel in the 2852 has a set of en-
hanced registers for control, monitoring and data
loading and unloading. The configuration register set
is compatible to those already available in the stan-
dard single 16C550 and dual ST16C2550. These
registers function as data holding registers (THR/
RHR), interrupt status and control registers (ISR/
IER), a FIFO control register (FCR), receive line sta-
tus and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable da-
ta rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR).
Beyond the general 16C2550 features and capabili-
ties, the 2852 offers enhanced feature registers (AFR,
EMSR, FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR,
TRG, FC) that provide automatic RTS and CTS hard-
ware flow control, Xon/Xoff software flow control, au-
tomatic RS-485 half-duplex direction output enable/
disable, FIFO trigger level control, FIFO level
counters, and simultaneous writes to both channels.
All the register functions are discussed in full detail
later in “UART INTERNAL REGISTERS” on page 18.
2.6 SIMULTANEOUS WRITE TO CHANNEL A AND B
During a write mode cycle, the setting of Alternate
Function Register (AFR) bit-0 to a logic 1 will override
the CHSEL selection and allows a simultaneous write
to both UART channel sections. This functional capa-
bility allow the registers in both UART channels to be
modified concurrently, saving individual channel ini-
tialization time. Caution should be considered, how-
ever, when using this capability. Any in-process serial
data transfer may be disrupted by changing an active
channel’s mode.
2.7 DMA MODE
The device does not support direct memory access.
The DMA Mode (a legacy term) in this document
doesn’t mean “direct memory access” but refers to
data block transfer operation. The DMA mode affects
the state of the RXRDY# A/B (MF# A/B becomes
RXRDY# A/B output when AFR[2:1] = ‘10’) and
TXRDY# A/B output pins. The transmit and receive
FIFO trigger levels provide additional flexibility to the
user for block mode operation. The LSR bits 5-6 pro-
vide an indication when the transmitter is empty or
has an empty location(s) for more data. The user can
optionally operate the transmit and receive FIFO in
the DMA mode (FCR bit-3=1). When the transmit and
receive FIFO are enabled and the DMA mode is dis-
abled (FCR bit-3 = 0), the 2852 is placed in single-
character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user
takes advantage of block mode operation by loading
or unloading the FIFO in a block sequence deter-
mined by the programmed trigger level. In this mode,
the 2852 sets the TXRDY# pin when the transmit
FIFO becomes full, and sets the RXRDY# pin when
the receive FIFO becomes empty. The following table
shows their behavior. Also see Figures 18
through 23.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
RXRDY# A/B
0 = 1 byte.
1 = no data.
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
0 = at least 1 byte in FIFO
1 = FIFO empty.
FCR Bit-3 = 1
(DMA Mode Enabled)
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B
0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
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