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PDF XR16L2450 Data sheet ( Hoja de datos )
| Número de pieza | XR16L2450 | |
| Descripción | 2.25V TO 5.5V DUART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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OCTOBER 2004
GENERAL DESCRIPTION
The XR16L2450 (L2450) is a dual universal asyn-
chronous receiver and transmitter (UART). The
XR16L2450 is an improved version of the
ST16C2450 with lower operating voltage and 5 volt
tolerant inputs. The L2450 provides enhanced UART
functions, a modem control interface and data rates
up to 1.5 Mbps. Onboard status registers provide the
user with error indications and operational status. In-
dependent programmable baud rate generators are
provided to select transmit and receive clock rates up
to 1.5 Mbps. An internal loopback capability allows
onboard diagnostics. The L2450 is available in a 44-
pin PLCC and 48-pin TQFP packages. The L2450 is
fabricated in an advanced CMOS process capable of
operating from 2.25 volt to 5.5 volt power supply with
5 volt tolerant inputs.
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FIGURE 1. XR16L2450 BLOCK DIAGRAM
XR16L2450
2.25V TO 5.5V DUART
FEATURES
REV. 1.1.0
• 2.25 to 5.5 Volt Operation
• 5 Volt Tolerant Inputs
• Pin-to-pin compatible to Exar’s ST16C2450,
ST16C2550, XR16L2550, XR16L2750 and
XR16C2850
• Pin-to-pin compatible to TI’s TL16C752B on the 48-
TQFP package
• 2 independent UART channels
■ Up to 1.5 Mbps data rate with a 24 MHz crystal
oscillator or external clock frequency
■ 1 byte Transmit FIFO
■ 1 byte Receive FIFO with error tags
■ Status report registers
■ Modem control signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
■ Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
• Crystal oscillator or external clock input
• TTL compatible inputs, outputs
• Industrial temperature ranges
• 48-TQFP and 44-PLCC packages
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
Reset
8-bit Data
Bus
Interface
*5V Tolerant inputs
UART Channel A
UART
Regs
THR
RHR
BRG
Modem I/Os
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
2.25 to 5.5 Volt VCC
TXA
RXA
RTSA#, CTSA#,
DTRA#, DSRA#,
CDA#, RIA#, OP2A#
TXB
RXB
RTSB#, CTSB#,
DTRB#, DSRB#,
CDB#, RIB#, OP2B#
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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REV. 1.1.0
XR16L2450
2.25V TO 5.5V DUART
PIN DESCRIPTIONS
NAME
44-PLCC
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
OP2B#
15
9 O Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when MCR[3] is set
to a logic 0. This output should not be used as a general output else it
will disturb the INTB output functionality. If it is not used, leave it uncon-
nected.
ANCILLARY SIGNALS
XTAL1
18
13 I Crystal or external clock input.
XTAL2
19
14 O Crystal or buffered clock output.
RESET
39
36 I Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will
reset the internal registers and all outputs. The UART transmitter output
will be held at logic 1, the receiver input will be ignored and outputs are
reset during reset period.
VCC
44
42 Pwr 2.25V to 5.5V power supply. All inputs are 5V tolerant.
GND
22
17 Pwr Power supply common, ground.
N.C.
1, 12, 23, 6, 12, 18,
- No Connection. These pins are not connected internally.
34 24, 25, 31,
37, 43
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
5
5 Page 
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REV. 1.1.0
XR16L2450
2.25V TO 5.5V DUART
2.12 Internal Loopback
The L2450 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 7 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 7. INTERNAL LOOP BACK IN CHANNELS A AND B
VCC
Transmit Shift Register
(THR/FIFO)
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
VCC
RTS#
CTS#
VCC
DTR#
DSR#
RI#
OP1#
VCC
OP2#
CD#
TXA/TXB
RXA/RXB
RTSA#/RTSB#
CTSA#/CTSB
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
OP2A#/OP2B#
CDA#/CDB#
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XR16L2450.PDF ] | |
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