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부품번호 | YGV619 기능 |
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기능 | Advanced Video Display Processor 6 | ||
제조업체 | LSI Computer Systems | ||
로고 | |||
YGV619
AVDP6
Advanced Video Display Processor 6
s Outline
YGV619 is a VDP (Video Display Processor) adopting OSD display control system which is best suited to the
data broadcasting. The digital image interface of this device for connection with MPEG decoder has been
improved. The use of this device allows screen composition that is suited to mobile information terminals, car
navigation system, etc. Scan timing conforming to the display standard of digital TVs can be made.
Two built-in PLL circuits allows to realize superimposition of external image signal on original image signal,
and to produce clock best suited to SDRAM that is adopted as external video memory.
s Features
q Display planes: External digital image is overlaid with OSD images composed of regions.
Up to four planes, which are individually composed of back drop plane (plane on which external images are inputted)
+ region, are available.
q OSD image format:
8bit/dot palette mode, and 16 bit RGB or YCbCr format can be selected.
YCbCr conforms to the conversion method of ITU601.
Color palette (256 colors in 16777 k colors) can be specified by region.
q Digital image input format:
· 18bitR6G6B6
(Max. dot clock frequency: 80 MHz)
· 16bitYCbCr422 (Max. dot clock frequency: 80 MHz)
· 8bitITU656
(Dot clock frequency 27 MHz)
q Digital image output format:
· R6G6B6 + 2 bit AT
· 18bitYCbCr444 + 2 bit AT
· 16bitYCbCr422 + 2 bit AT
· 8bitITU656 + 2 bit AT + 6 bit α blending coefficient
q Max. OSD resolution: 960 dots × 1080 lines
(However, max. resolution of overlaid external image is 1920 ×1080 lines)
q Applicable digital TV image format:
· 525i
· 525p
· 1125i
q Video capture function:
· Draws external image input on the frame memory in real time.
· Can convert resolution.
· Provided with progressive scanning conversion
YGV619 CATALOG
CATALOG No.: LSI-4GV619A1
2001.01
s Pin Assignment
AVSS1
AVDD1
A23
A22
A21
A20
A19
VSS
A18
VDD
A17
A16
A15
A14
A13
A12
A11
A10
A9
VSS
A8
A7
A6
A5
VDD
A4
A3
A2
A1/W R 3
WR2
WR1
VSS
WR0
RD
RESET
VDD
CSREG
CSMEM
LWD
LEND
SYCKS
DREQ
VSS
READY
WAIT
INT
D31
VDD
D30
D29
D28
D27
D26
D25
D24
VSS
D23
D22
D21
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Top view
YGV619
180 VDD
179 DRO1
178 DRO2
177 VSS
176 DRO3
175 DRO4
174 DRO5
173 GCKOUT
172 AT0
171 VSS
170 AT1
169 FSC
168 BLANK
167 HSYNC
166 CSYNC
165 VDD
164 SDQ24
163 VSS
162 SDQ23
161 SDQ25
160 SDQ22
159 SDQ26
158 SDQ21
157 VSS
156 SDQ27
155 SDQ20
154 SDQ28
153 SDQ19
152 VDD
151 SDQ29
150 VSS
149 SDQ18
148 SDQ30
147 SDQ17
146 SDQ31
145 SDQ16
144 VSS
143 DQM3
142 DQM2
141 SA4
140 SA3
139 VDD
138 SA5
137 SA2
136 SA7
135 VSS
134 SA6
133 SA1
132 SA0
131 SA8
130 SA10
129 SA9
128 SA12
127 VDD
126 SBA0
125 VSS
124 SA11
123 SBA1
122 SCS
121 RAS
4
4페이지 YGV619
l RAS (O)
Outputs row address strobe signal for SDRAM.
When two 16 bit SDRAMs are used, connect this pin to both SDRAMs.
l CAS (O)
Outputs column address strobe signal for SDRAM.
When two 16 bit SDRAMs are used, connect this pin to both SDRAMs.
l WE (O)
Outputs write strobe signal for SDRAM.
When two SDRAMs are used, connect this pin to both SDRAMs.
l DQM3-0 (O)
Outputs data mask signal for SDRAM. DQM3, DQM2, DQM1 and DQM0 are mask control signals for SDQ31-24,
SDQ23-16, SDQ15-8 and SDQ7-0 respectively. When masking the data, corresponding DQM pin outputs high level
signal.
When one 16 bit SDRAM is used, DQM3-2 pins are not used, thus they are to be kept open.
l SDCLK (I/O)
Outputs CLK for SDRAM. SDCLK inputs the clock once outputted from this pin to use it as fetch clock to obtain
setup time at SDQ input.
< Display monitor interface >
l R, G, B (O: analog output)
Outputs linear RGB signal. Termination resistor of 37.5Ω is connected to this pin to make the resolution of output
voltage amplitude 8 bits. Monitor with impedance of 75Ω can be driven directly through this interface as shown below.
R(G,B)
RL=75Ω
RL=75Ω
l REXT (I: analog input)
A resistor is connected between this pin and GND(AVSS4) for adjusting the amplitude of signal outputted from DAC
for RGB. The standard amplitude of signal outputted from DAC is 0.7 V (rREXT=470 Ω). The amplitude of the output
can be adjusted finely within around ±100Ω by using the following formula.
Vp_p = 470 × 0.7 / rREXT
l CSYNC (O)
Outputs composite sync signal for external monitor. In interlaced scanning mode, equalizing pulses are added to this
signal. This pin can output VSYNC by using internal register setting.
l HSYNC (O)
Outputs horizontal sync signal for external monitor.
l BLANK (O)
Outputs a signal that indicates effective display period when LCD panel is connected to the device.
l AT1-0 (O)
AT1-0 bits of display data are outputted from these pins.
l FSC (O)
Outputs subcarrier clock for video encoder. The subcarrier clock is created by dividing the clock inputted to DCKIN
pin by 1, 2, 4, or 8, which is determined by register setting. For example, inputting 14.318 MHz to DCKIN pin and
dividing it by “4” give subcarrier clock of 3.58 MHz.
7
7페이지 | |||
구 성 | 총 15 페이지수 | ||
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |