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PDF Z86C95 Data sheet ( Hoja de datos )
| Número de pieza | Z86C95 | |
| Descripción | CMOS Z8 DIGITAL SIGNAL PROCESSOR (DSP) | |
| Fabricantes | Zilog. | |
| Logotipo |  |
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Z86C95 DSP
CPS DC-4067-13
CUSTOMER PROCUREMENT SPECIFICATION
GENERAL DESCRIPTION
The Z86C95 MCU (Microcontroller Unit ) introduces a new
level of sophistication to Superintegration™ ICs. The
Z86C95 is a member of the Z8® single-chip microcontroller
family incorporating a CMOS ROMless Z8 microcontroller
with an embedded DSP processor for digital servo control.
The DSP slave processor can perform 16-bit x 16-bit
multiplicates and accumulates in one clock cycle. Addi-
tionally, the Z86C95 is further enhanced with a hardwired
16-bitx16-bit multiplier and a 32-bit/16-bit divider, three
16-bit counter timers with capture and compare registers,
a half flash 8-channel 8-bit A/D converter with a 2 µsec
conversion time, an 8-bit DAC with 1/4 programmable gain
stage, UART, serial peripheral interface, and a PWM
output channel (Functional Block Diagram). It is fabricated
using CMOS technology and offered in an 80-pin QFP, 84-
pin PLCC, or 100-pin VQFP package.
The Z86C95 provides up to 16 output address lines thus
permitting an address space of up to 64 Kbytes of data and
program memory each. Eight address outputs (AD7-AD0)
are provided by a multiplexed, 8-bit, Address/Data bus.
The remaining 8 bits are provided via output address bits
A15-A8.
Z86C95
CMOS Z8® DIGITAL
SIGNAL PROCESSOR (DSP)
There are 256 registers located on chip and organized as
236 general-purpose registers, 16 control and status reg-
isters, and four I/O port registers. The register file can be
divided into sixteen groups of 16 working registers each.
Configuration of the registers in this manner allows the use
of short format instructions; in addition, any of the indi-
vidual registers can be accessed directly. Also, the Z86C95
contains 512 bytes of DSP Program RAM and 128 words
of DSP data RAM.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
V
CC
GND
V
DD
V
SS
OPERATING ERRATA
This notice only applies to devices top marked "Z86C9524
ASC/FSC/VSC" with a date code of 9237 or later.
The following operating errata only applies to devices
topmarked with "Z86C95 ASC/FSC/VSC."
1. A DSP load to the DAC Register fails below approxi-
mately VCC = 4.7V.
2. Clipping occurs in the linearity of the DAC with a 100K
load at about 3.3V output (VDHI = 3.5V).
3. ICC1 at HALT Mode will show a current of 17-18 mA,
then will jump to 40-70 mA, and will settle between 17-
24 mA. Settling time is about 10-15 seconds.
4. ICC2 at STOP Mode and DSP Pause will show a current
of 1-2 mA, then will jump to 5-7 mA, and will settle at 3-
4 mA. Settling time is about 10-15 seconds.
1. ICC1 at HALT Mode will show a current of 17-18 mA,
then will jump to 40-70 mA, and will settle between 17-
24 mA. Settling time is about 10-15 seconds.
2. ICC2 at STOP Mode and DSP Pause will show a
current of 1-2 mA, then will jump to 5-7 mA, and will
settle at 3-4 mA. Settling time is about 10-15 seconds.
The following operating errata only applies to devices
topmarked with "Z86C9540 ASC/FSC/VSC or SL 1636."
1. ICC1 at HALT Mode will show a current of 17-18 mA,
then will jump to 40-70 mA, and will settle between 17-
24 mA. Settling time is about 10-15 seconds.
DC-4067-13 (5-17-94)
1
1 page  
PIN DESCRIPTION (Continued)
Z86C95 DSP
CPS DC-4067-13
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
VSS
VDD
NC
D0
D1
SK
SLAVESEL
DSP_RW
DSP_SYNC
C02
C01
DSP_SSN
/WAIT
50
55
60
65
70
75
45 40 35 30
Z86C95
100-Lead VQFP
80 85 90 95
25 NC
SYNC
SCLK
NC
20 RESET
PWM
XTAL2
XTAL1
P30
15 P31
P32
P33
P35
P36
10 P37
VDD
VDHI
DAC
VDLO
5 ANA7
ANA6
ANA5
ANA4
NC
1 NC
100-Pin VQFP Pin Assignments
5
5 Page 
AC CHARACTERISTICS
External I/O or Memory Read and Write; DSR/DSW; WAIT Timing Table
No Sym
Parameter
TA = 0°C to +70°C
40 MHz**
33 MHz
24 MHz
Min Max Min Max Min Max
1 TdA(AS)
2 TdAS(A)
3 TdAS(DI)
4 TwAS
Address Valid To /AS Rise Delay
/AS Rise To Address Hold Time
/AS Rise Data In Req’d Valid Delay
/AS Low Width
8
15
10
5 TdAZ(DSR) Address Float To /DS Fall (Read)
0
6 TwDSR
/DS (Read) Low Width
60
7 TwDSW
/DS (Write) Low Width
35
8 TdDSR(DI) /DS Fall (Read) To Data Req'd Valid Delay
9 ThDSR(DI)
10 TdDS(A)
11 TdDS(AS)
12 TdR/W(AS)
/DS Rise (Read) to Data In Hold Time
/DS Rise To Address Active Delay
/DS Rise To /AS Delay
R/W To Valid /AS Rise Delay
0
20
16
10
13 TdDS(R/W) /DS Rise To R/W Not Valid Delay
14 TdDO(DSW) Data Out To /DS Fall (Write) Delay
15 ThDSW(DO) /DS Rise (Write) To Data Out Hold Time
16 TdA(DI)
Address Valid To Data Req’d Valid Delay
12
12
12
17 TdAS(DSR)
19 TdDM(AS)
20 TdDS(DM)
/AS Rise To /DS Fall (Read) Delay
/DM Valid To /AS Rise Delay
/DS Rise To /DM Valid Delay
20
10
15
21 ThDS(A)
/DS Rise To Address Valid Hold Time
22 TdXT(SCR) XTAL Falling to SCLK Rising
23 TdXT(SCF) XTAL Falling to SCLK Falling
24 TdXT(DSRF) XTAL Falling to/DS Read Falling
15
25 TdXT(DSRR) XTAL Falling to /DS Read Rising
26 TdXT(DSWF) XTAL Falling to /DS Write Falling
27 TdXT(DSWF) XTAL Falling to /DS Write Rising
28 TsW(XT)
Wait Set-up Time
29 ThW(XT)
Wait Hold Time
30 TwW
Wait Width (One Wait Time)
5
15
20
15
20
75
15
0
65
40
40
0
25
16
12
12
12
12
90
20
10
15
15
30
30
40
30
40
30
5
15
20
22
25
96 130
28
0
100
65
45 80
0
40
30
26
30
34
34
115 160
40
22
35
30
35 40
35 40
45 50
35 45
45 50
35 45
5
15
25
Notes:
When using extended memory timing add 2 TpC.
Timing numbers given are for minimum TpC.
** Preliminary values, to be characterized.
Z86C95 DSP
CPS DC-4067-13
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet Z86C95.PDF ] | |
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