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PDF Z89393 Data sheet ( Hoja de datos )
| Número de pieza | Z89393 | |
| Descripción | 16-BIT DIGITAL SIGNAL PROCESSORS | |
| Fabricantes | Zilog. | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de Z89393 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
PRELIMINARY
CUSTOMERPROCUREMENTSPECIFICATION
FEATURES
DSP ROM OTP DSP RAM Max Core
Device (K Words) (K Words) (Words)
MIPS
Z89323
8
512
Z89373
8 512
Z89393 64*
512
* External
s Operating Temperature Ranges:
0°C to +70°C (Standard)
–40°C to +85°C (Extended)
20
16
20
s 4.5- to 5.5-Volt Operating Range
DSP Core
s 20 MIPS @ 20 MHz, 16-Bit Fixed Point DSP
s 50 ns Instruction Cycle Time
s Single-Cycle Multiply and ALU Operations
s Two Internal Data Buses and Address Generators
s Six Register Address Pointers
s Optimized Instruction Set (30 Instructions)
Z89323/373/393
16-BITDIGITAL
SIGNALPROCESSORS
Package 44-Pin 68-Pin 44-Pin 80-Pin 100-Pin
Device PLCC PLCC QFP QFP QFP
Z89323
Z89373
Z89393
On-Board Peripherals
s 4-Channel, 8-Bit Analog to Digital Converter (A/D)
s On-Board Serial Peripheral Interface (SPI)
s Up to 40 Bits of Programmable I/O
s Two Channels of Programmable
Pulse Width Modulators (PWM)
s Three General-Purpose Timer/Counters
s Two Watch-Dog Timers (WDT)
s Programmable PLL
s Three Vectored Interrupts Servicing Eight
Interrupt Sources
s Power-Down and Power-On Reset
GENERAL DESCRIPTION
The Z89323/373/393 DSP family of products builds on
Zilog's first generation Z893XX DSP core, integrating several
peripherals especially well suited for cost-effective voice,
telephony, and control applications.
These DSP devices feature a modified Harvard architecture
supported by one program bus and two on-chip data
buses. This bus structure is supported by two address
generators and six register pointers to ensure that the
20 MIPS DSP CPU is continually active.
The Z893X3 DSP family is designed to provide a complete
DSP and control system on a single chip. By integrating
various peripherals, such as a high-speed 4-channel, 8-bit
A/D, an SPI, three timers with PWM and WDT support, the
Z893X3 family provides a compact system solution and
reduces overall system cost.
To support a wide variety of development needs, the
Z893X3 DSP product family features the cost-effective
Z89323 with 8 Kwords of on-chip ROM, and the Z89373, a
16-MIPS OTP version of the Z89323, ideal for prototypes
and early production builds. For systems requiring more
than 8 Kwords of program memory, the Z89393 device can
address up to 64 Kwords of external program memory.
DS95DSP0101 Q4/95
1
1 page  
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Table 2. 68-Pin PLCC Z89323/373 Pin Description
No. Symbol
1 P12/SIN
2 P20/INT0
3 EXT12/P012
4 EXT13/P013
5 VDD
6 EXT14/P014
7V
SS
8 EXT15/P015
9 NC
10 NC
11 EXT3/P03
12 EXT4/P04
13 V
SS
14 V
DD
15 EXT5/P05
16 P13/SOUT
17 EXT6/P06
18 P14/SS
19 EXT7/P07
20 P15/SK
21 P27
22 EXT8/P08
23 EXT9/P09
24 VSS
25 EXT10/P010
26 V
SS
27 EXT11/P011
28 VDD
29 VAHI
30 V
SS
31 P16/UI0
32 VALO
33 P17/UI1
34 ANGND
Function
Port12/SerialInput
Port20/Interrupt0
ExtData12/Port012
ExtData13/Port013
Power
ExtData14/Port014
Ground
ExtData15/Port015
NoConnection
NoConnection
ExtData3/Port03
ExtData4/Port04
Ground
Power
ExtData5/Port05
Port13/SerialOutput
ExtData6/Port06
Port14/SerialSelect
ExtData7/Port07
Port15/SerialClock
Port27
ExtData8/Port08
ExtData9/Port09
Ground
ExtData10/Port010
Ground
ExtData11/Port011
Power
AnalogHighRef.
Ground
Port16/UserInput0
AnalogLowRef.
Port17/UserInput1
AnalogGround
Direction
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
Input
In/Output
Input
In/Output
Input
No. Symbol
Function
35 AN0
36 AN1
37 AN2
38 AN3
39 VSS
40 P21/INT1
41 ANVCC
42 VDD
43 RD//WR
44 HALT
A/DInput0
A/DInput1
A/DInput2
A/DInput3
Ground
Port21/Interrupt1
AnalogPower
Power
R/WExternalBus
HaltExecution
45 EA0
46 EA1
47 EA2
48 NC
49 V
DD
50 P23/UO1
51 /DS
52 P24/UO2
53 CLKI
54 CLKO
ExtAddress0
ExtAddress1
ExtAddress2
NoConnection
Power
Port23/UserOutput1
ExtDataStrobe
Port24/UserOutput2
Clock/CrystalIn
Clock/CrystalOut
55 P26
56 P22/UO0
57 P25/UI2
58 WAIT
Port26
Port22/UserOutput0
Port25/UserInput2
WaitforExt
59 /RES
60 V
SS
61 V
DD
62 VSS
63 EXT0/P00
Reset
Ground
Power
Ground
ExtData0/Port00
64 EXT1/P01
ExtData1/Port01
65 EXT2/P02
ExtData2/Port02
66 P10/INT2
Port10/Interrupt2
67 V
Ground
SS
68 P11/CLKOUT Port11/ClockOutput
Direction
Input
Input
Input
Input
In/Output
Input
Input
Output
Input
Output
Output
Output
In/Output
Output
In/Output
Input
Input
In/Output
In/Output
In/Output
Input
Input
In/Output
In/Output
In/Output
In/Output
In/Output
DS95DSP0101 Q4/95
5
5 Page 
PIN FUNCTIONS
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
CLKO-CLKI Clock (output/input). These pins act as the Priority is: INT2 = lowest, INT0 = highest. (Note: INT2 pin
clock circuit input and output.
is not bonded out on the 44-pin QFP or PLCC packages.)
EXT15-EXT0 External Data Bus (input/output). These pins
act as the data bus for user-defined outside registers, such
as an ADC or DAC. The pins are normally tri-stated, except
when the outside registers are specified as destination
registers in the instructions. All the control signals exist to
allow a read or a write through this bus. If user I/O Port 0
is enabled, these signals function as user Programmable
I/O.
RD//WR Read/Write Strobe (output). This pin controls the
data direction signal for the EXT-Bus. Data is available
from the CPU on EXT15-EXT0 when this signal is Low. EXT-
Bus is in input mode (high-impedance) when this signal is
High.
/RES Reset (input, active Low). This pin controls the
asynchronous reset signal. The /RES signal must be kept
Low for at least one clock cycle (clock output of the PLL
block). The CPU pushes the contents of the Program
Counter (PC) onto the stack and then fetches a new PC
value from program memory address 0FFCH (or FFFCH for
the Z89393) after the reset signal is released.
WAIT WAIT State (input). The wait signal is sampled at the
rising edge of the clock with appropriate setup and hold
times. The normal write cycle will continue when wait is
inactive on a rising clock. A single wait-state can be
generated internally by setting the appropriate bits in the
wait state register (Bank 15/Ext 3) (active high).
EA2-EA0 External Address (output). These pins control
the user-defined register address output (latched). One of
eight user-defined external registers is selected by the
processor with these address pins for read or write
operations. Since the addresses are part of the processor
memory map, the processor is simply executing internal
reads and writes. External Addresses are used internally
by the processor if the ADC, bit I/O (Port 0- 2), or SPI are
enabled. (See the banks allocation of the EXT registers in
Tables 6 and 7.)
P00-P015 Port 0 (input/output). These pins control Port 0
input and output when EXT I/F is not in use.
P10-P17 Port 1 (input/output). These pins are used for
Port 1 programmable bit I/O when INT2, CLKOUT, SPI, or
UI0-1 are not being used.
P20-P27 Port 2 (input/output). These pins control Port 2
input or output when UI2, UO0-2 or INT0-INT1 are not
being used.
/DS Data Strobe (output). This pin control the data strobe
signal for EXT-Bus. Data is read by the external peripheral
on the rising edge of /DS. Data is also read by the
processor on the rising edge of CK.
HALT Halt State (input). This pin controls Stop Execution.
The CPU continuously executes NOPs and the program
counter remains at the same value when this pin is held
High. An interrupt request must be executed (enabled) to
exit HALT mode. After the interrupt service routine, the
program continues from the instruction after the HALT
(active high).
/INT0-/INT2 Three Interrupts (input, active on rising edge).
These pins control interrupt requests 0-2. Interrupts are
generated on the rising edge of the input signal. Interrupt
vectors for the interrupt service starting address are stored
in the following program memory locations:
Device
Z89323/373
Z89393
/INT0
1FFFH
FFFFH
/INT1
1FFEH
FFFEH
/INT2
1FFDH
FFFDH
P30-P37 Port 3 Port3 (3:0) are four inputs and P3 (7:0) are
four outputs.
UI1-UI0 Two Input Pins (input). These general-purpose
input pins are directly tested by the conditional branch
instructions. These are asynchronous input signals that
have no special clock synchronization requirements.
UO1-UO0 Two Output Pins (output). These general-
purpose output pins reflect the value of two bits in the
status register S5 and S6. These bits have no special
significance and may be used to output data by writing to
the status register. Note: The user output value is the
opposite of the status register content.
SIN/SOUT. When enabled, these pins control SPI input
and output.
AN0-AN3. These pins are used for Analog-to-Digital
converter input.
ANGND and ANVCC. Analog to Digital ground and power
supply.
DS95DSP0101 Q4/95
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet Z89393.PDF ] | |
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