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기능 GENERAL-PURPOSE EMBEDDED CONTROLLERS
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Z8L18920FSC 데이터시트, 핀배열, 회로
Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
PRELIMINARY PRODUCT SPECIFICATION
FEATURES
Part
Z80189
Z8L189
CPU
S180*
S180*
UART
16550
16550
I/O Speed (MHz)
24 33
24 20
s Fully Static Z180MPU Core*
– On-Chip 1 MByte MMU
– Two Enhanced UART Channels (up to 512 Kbps)†
– Two Chain-Linked DMA Channels†
– x 2 Clock Multiplier
– Low-Power Consumption Modes
– Two 16-Bit Timer/Counters
– Clocked Serial I/O
– On-Chip Wait State Generator (WSG)
– On-Chip Interrupt Controller
On-Chip Clock Oscillator/Generator
s 16550 Compatible MIMIC Interface
– 16 mA MIMIC Output Drive Capability
Z80189/Z8L189
GENERAL-PURPOSE
EMBEDDED CONTROLLERS
s Com Port Decode
s PC DMA Mailbox Registers
s Host I/O Mailbox
s Programmable Fixed /ROMCS and
/RAMCS Boundaries
s 100-Pin QFP and VQFP Packages
s 3.3 and 5.0-Volt Operating Ranges
s 0°C to +70°C Temperature Range
Notes:
† Enhancements from the Discrete S180 device.
GENERAL DESCRIPTION
The Z80189/Z8L189 are cost-effective modem controllers
that address a new generation of data pumps having the
HDLC formatting feature. Data pumps of these types do
not require an HDLC interface; therefore, the Z80189 does
not need the ESCC. The addition of the PC DMA Mailbox
Registers allow DMA data transfer between the PC memory
and the modem speaker/microphone CODEC. The Z80189
is a smart peripheral controller chip for modem (in particu-
lar V.34 applications), fax, voice messaging, and other
communications applications.
The Z80189/Z8L189 consists of an enhanced Z8S180
microprocessor, a 16550 MIMIC with increased MIMIC
drive capability for direct connection to the IBM PC, XT, AT
bus, and 24 bits of parallel I/O. Current PC modem soft-
ware compatibility can be maintained with the Z80189's
ability to mimic the 16550 UART chip. The Z80180 core is
the intelligent controller between the data pump and
16550 MIMIC interface when used in internal applications.
This intelligent controller performs the data compression
and error correction on outgoing and incoming data.
The integration of COM Port Decode circuitry to the Z80189
allows the MIMIC to be selected for a specific COM Port
Address (PC COM Port Address 1-4). COM Port Decode
circuitry is simplified by allowing the user to select the
MIMIC COM Port addresses through software, in addition
to eliminating the need for external circuitry required for
COM Port Decode logic.
The PC DMA and I/O Mailbox Interface can be used to
provide communication paths between the PC Host and
the Z80189. These new communication paths can be used
for voice, DTAD, or jumperless COM Port selection.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Power
Ground
Circuit
VCC
GND
Device
VDD
VSS
DS971890301
1




Z8L18920FSC pdf, 반도체, 판매, 대치품
Zilog
PIN DESCRIPTION (Continued)
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
/HDDIS/TXA0
HA0
HA1/RXA0
HA2
/HCS/HC1
/HALT
HA3//RFSH
/IORQ
/MRD//MREQ
/IOCS2/E
/M1
/WR
/RD
PHI
VSS
XTAL
EXTAL
HA4//WAIT
HDRQ1//BUSACK
/HDACK1//BUSREQ
/RESET
/NMI
/INT0
/INT1/PC6
/INT2/PC7
75
76
80
85
90
95
100
1
70 65 60
Z80189/Z8L189
100-Pin VQFP
5 10 15
55
20
51
50
45
40
35
30
26
25
EV1
/ROMCS
/RAMCS
HDRQ0/RTS0
VDD
HA5//DREQ1
HC2/CKS
HINTR1/TOUT
HA9/CKA1//TEND0
VSS
/HDACK0/CKA0//DREQ0
PB7/RXS//CTS1
PB6/RXA1
PB5/TXA1
PB4/RXA0
PB3/TXA0
PB2//DCD0
PB1//CTS0
PB0/TXS
D7
D6
D5
D4
D3
D2
Figure 3. Z80189/Z8L189 100-Lead VQFP Pin Identification
4 DS971890301

4페이지










Z8L18920FSC 전자부품, 판매, 대치품
Zilog
TIMING DIAGRAMS
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Opcode Fetch Cycle
T1
4
2
ø
T2 TW
5
3
T3
Address
/WAIT
1
6
20
19 19
20
/MREQ
/IORQ
7
8
12
/RD
9
/WR
/M1
14
10 18
I/O Write Cycle †
I/O Read Cycle †
T1 T2 TW T3
11
7
11
13 28
29
13
9
22 25
26 and 26a
T1
11
11
ST
Data
IN
Data
OUT
62
/RESET
68
17
63
67
15 16
23
15
24
62
67
16
21
27
63
68
Figure 5. CPU Timing
(Opcode Fetch Cycle, Memory Read/Write Cycle I/O Read/Write Cycle)
DS971890301
7

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