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ZL10310 데이터시트 PDF




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부품번호 ZL10310 기능
기능 Digital Television DVB-T-On-a-Chip Processor
제조업체 Zarlink Semiconductor Inc
로고 Zarlink Semiconductor Inc 로고


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ZL10310 데이터시트, 핀배열, 회로
Features
• DTV-SoC for Digital Terrestrial Television (DTT)
• On-chip DVB-T COFDM demodulator with FEC.
• 6 Video DACs on-chip, for Composite or
Component (RGB or Y U/V) Analog Video
• Twin PAL/NTSC DENCs
• Low Power (<1.4W Typical)
• Low Component Count
• Unified SDRAM controller
• I2S Digital Audio Input
• I2S and S/PDIF Digital Audio outputs
• MPEG-2 Audio & Video decoders
• PowerPC 405TM CPU Core with 16k/16k cache,
Memory manager and Virtual memory system
• Complete Linux-based Software Development Kit
(SDK)
• IDE interface
• Inputs for external MPEG-2 Transport Streams,
allowing support for external demodulators (e.g.
Cable TV, Satellite TV)
• Conditional Access (CA) DVB-descrambler
ZL10310/ZL10311
Digital Television DVB-T-On-a-Chip
Processor
Data Sheet
Issue 1.0
November 2002
Ordering Information
ZL10310/GAC 388 ball EPBGA
ZL10311/GAC 388 ball EPBGA
00C to +700C
• Smart Card Interface
• Infrared & UART interface
• DVB-compatible Common Interface (CI) control
and bitstream interfaces
• Multi-stream multiplexing to support internal and
external demodulators
• External Modem support interface
• Supports MacrovisionTM Copy Protection -
(ZL10311 only; available to Macrovision license
holders only)
• DolbyDigital* Decoding - (ZL10311 only;
available to DolbyDigital* license holders only -
*awaiting certification)
De-mod
/JTAG
ADC IN
/De-mod
AGC B
Flash
IDE
CI Control
Smart Card
CODEC/modem
I2C
UART/IRDA
BIT I/O
Bitstream
O/P
/Second Bitstream
Smart Card I/P
ZL10310 / ZL10311 DTV-SOC
EXTIN
JTAG
Bitstream
Multiplexing &
Control
De-
scrambler
ADCIN
COFDM
DeModulator
& FEC
AUX Bus
Cached
PowerPCR 405
Sub System
Peripherals
Power Management
8k Boot
ROM
SDRAM
Controller
SDRAM
Controller
Audio
Decoder
System
DeMultiplex
I 2S
Stereo Audio
DAC
S/PDIF
Video
Decoder
Video Scaler
/ Blender
Comp
Video Video
DENCs
/DACs
Y+U/V
RGB
Analog
Video
SDRAM 1
BUS
SDRAM 0
BUS
(optional)
Figure 1 - Block Diagram of ZL10310 and ZL10311
1




ZL10310 pdf, 반도체, 판매, 대치품
ZL10310/ZL10311
Data Sheet
1.0 Device Overview
Zarlink Semiconductor has designed the ZL10310 and ZL10311 System On a Chip (SoC) devices specifically for
DVB-T applications. Integrating a high performance PowerPC 405TM processor with robust industry proven
MPEG-2 audio and video decoding, OSD and a COFDM demodulator, the ZL10310 and ZL10311 deliver the
performance and functionality required for advanced Digital TV entertainment products. It enables the rapid design
and manufacture of cost-effective iDTV and Digital Audio Visual Home Entertainment Centers.
The enhanced ZL10311 also supports DVD playback with up to six DolbyDigital1 audio channels. In addition, by
integrating the COFDM demodulator, the ZL10310 and ZL10311 enable the implementation of very small footprint
TV Adaptor modules.
2.0 Device Interfaces
The following peripheral interfaces are available to the user. Apart from possible level translation and connector
buffering, no external devices are required to support any of the interfaces.
• 10-bit input that may be configured for an ADC input to the internal COFDM demodulator
• Additional input bus for additional MPEG-2 Transport Sources
• AGC (PWM) outputs for a terrestrial tuner
• Serial control port for a digital tuners
• Common interface control and bitstream interfaces for an external descrambler
• Normal PC (PCMCIA) memory module interface for local software updates
• Unified 64 Mbit SDRAM interface for all decoders and PowerPC 405TM
• Additional SDRAM interface for high end systems requiring increased memory bandwidth
• Static memory interface for Flash and external peripherals
• IDE/ATAPI interface for hard disk and DVD drives
• External DMA channel and interrupts
• Six analog video outputs give full flexibility on RGB, S-VHS, and composite signals (with and without OSD)
• I2S input port from external Digital Stereo source
• Three I2S ports to external audio DACs for main, surround, and centre channels
• Dolbysurround sound control signals
• Sony/Philips Digital InterFace (S/PDIF)
If not required in a particular system, any of the peripheral interfaces can be replaced by individual I/O bits from
internal general purpose registers. These can then be used for additional purpose, such as interfacing to switches
and displays.
• Full RS232 interface to an external modem or a 4 wire interface to a Codec
• IRDA interface or an additional asynchronous serial interface
• Synchronous serial interface for EEPROM, etc.
• Two Smart card Interfaces (one instead of a Common Interface)
• General purpose I2C interface
• General purpose timer for Infrared (IR) decoding
• General purpose individual bit I/Os
1. The ZL10311 device is awaiting Dolby Certification
4 Zarlink Semiconductor Inc.

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ZL10310 전자부품, 판매, 대치품
Data Sheet
ZL10310/ZL10311
4.3 Coded Orthogonal Frequency Division Multiplex (COFDM) Demodulator
The COFDM demodulator is used to demodulate a digitized COFDM modulated IF signal from the TV Tuner, and
ultimately convert the resulting MPEG-2 Transport Stream to the MPEG-2 demultiplexer.
The Digitized IF is converted to a complex Baseband signal centered on zero frequency. It also removes adjacent
channel interference prior to a Time-to-Frequency Fast Fourier Transform (FFT). The resulting signals are then sent
to a digital re-timing block, symbol sync, carrier recovery, and timing recovery. An AGC signal, with a variable mark
space ratio, is provided to control the signal levels in the tuner sections of the receiver. Forward Error Correction
(FEC) is performed by Viterbi decoding of the convolutional coded data, followed by de-interleaving, Reed-Solomon
decoding, and energy dispersal de-randomising. The output is MPEG-2 Transport Stream packets, in byte format.
The COFDM demodulator is fully compliant with the ETSI 300 744 and Digital Television Group (DTG)
specifications. Key features are:
• FFT processor operates in 2k and 8k carrier mode.1
• All hierarchical and non-hierarchical constellations.
• Automatic digital carrier recovery over a wide range of offsets without the need for AFC
• Automatic digital carrier recovery without the need for a VCXO
• Common phase error correction
• Channel correction using time and frequency filtering
• Automatic co - channel protection, frame sync, and fast channel re- acquisition
• Internal controller handles all tracking and acquisition
• Viterbi decoding with code rates of 1/2, 2/3, 3/4, 5/6, 6/7, and 7/8
• Automatic synchronization and code rate detection
• Constraint length K = 7
• Trace back depth of 128
• De-interleaver followed by DVB Reed Solomon error correction
• De-randomizer and common interface formatting
4.4 MPEG Audio Decoder
The MPEG Audio Decoder produces dual channel outputs from MPEG -1 or MPEG -2 Transport Streams with a
maximum rate of 640 kbit/sec. It supports sampling rates of 32, 44.1, and 48 KHz, plus the half rate options. All
sampling rates, plus 512/256 Fs, are produced from an internal PLL. A version of the device is available which
produces six channels of audio output for holders of the DolbyDigital2 License.
• Decodes MPEG-1 and dual channel MPEG-2 audio
• Performs MPEG-1 audio parsing and MPEG-2 Packetised Elementary Stream (PES) audio parsing, or
accepts audio elementary streams
• Supports 32kHz, 44.1 kHz, and 48 kHz sampling rates plus the half rate options
• All sampling rates, plus 512/256 Fs, derived from an internal PLL
• 64 step audio attenuation with smooth step transitions
• SPDIF output meeting IEC1937 specifications
• Re-locatable ancillary data region
• Audio Clip Mode
• DolbyAC3 option2
1. For details on 8k carrier performance and use, please consult Zarlink Field Applications
2. The ZL10311 device is awaiting Dolby Certification
Zarlink Semiconductor Inc.
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
ZL10310

Digital Television DVB-T-On-a-Chip Processor

Zarlink Semiconductor Inc
Zarlink Semiconductor Inc
ZL10311

Digital Television DVB-T-On-a-Chip Processor

Zarlink Semiconductor Inc
Zarlink Semiconductor Inc

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