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ZL50233GD 데이터시트 PDF




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부품번호 ZL50233GD 기능
기능 4 Channel Voice Echo Cancellor
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ZL50233GD 데이터시트, 핀배열, 회로
ZL50233
4 Channel Voice Echo Cancellor
Data Sheet
Features
• Independent multiple channels of echo
cancellation; from 4 channels of 64ms to 2
channels of 128ms with the ability to mix
channels at 128ms or 64ms in any combination
• Independent Power Down mode for each group of
2 channels for power management
• Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
• Passed AT&T voice quality testing for carrier
grade echo cancellers.
• Compatible to ST-BUS and GCI interfaces with
2Mb/s serial PCM data
• PCM coding, µ/A-Law ITU-T G.711 or sign
magnitude
• Per channel Fax/Modem G.164 2100Hz or G.165
2100Hz phase reversal Tone Disable
• Per channel echo canceller parameters control
• Transparent data transfer and mute
• Fast reconvergence on echo path changes
• Fully programmable convergence speeds
• Patented Advanced Non-Linear Processor with
high quality subjective performance
March 2003
Ordering Information
ZL50233/QCC 100-Pin LQFP
ZL50233/GDC 208-Ball LBGA
-40°C to +85°C
• Protection against narrow band signal divergence
and instability in high echo environments
• 0 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
• Offset nulling of all PCM channels
• 10 MHz or 20 MHz master clock operation
• 3.3 V I/O pads and 1.8V Logic core operation with
5-Volt tolerant inputs
• IEEE-1149.1 (JTAG) Test Access Port
• ZL50232, ZL50233, ZL50234 and ZL50235 have
same pinouts in both LQFP and LBGA packages
Applications
• Voice over IP network gateways
• Voice over ATM, Frame Relay
Rin
Sin
MCLK
Fsel
C4i
F0i
VDD1 (3.3V)
VSS
VDD2 (1.8V)
ODE
Serial
to
Parallel
PLL
Timing
Unit
Echo Canceller Pool
Group 0 Group 1
ECA/ECB ECA/ECB
Microprocessor Interface
Parallel
to
Serial
Note:
Refer to Figure 4
for Echo Canceller
block diagram
Test Port
Rout
Sout
RESET
DS CS R/W A10-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST
Figure 1 - ZL50233 Device Overview
1




ZL50233GD pdf, 반도체, 판매, 대치품
ZL50233
Data Sheet
Pin Description
PIN
Name
PIN #
208-Ball LBGA
100 PIN
LQFP
Description
VSS A1, A3,A7,A11, A13, 5, 18, 32, Ground.
A15, A16, B2, B6, B8, 42, 56, 69,
B12, B14, B15, B16, C3, 81, 98
C5, C7, C9, C11, C12,
C13, C14, C16, D4, D8,
D10, D12, D13, E3, E4,
E14, F13, G3, G4, G7,
G8, G9, G10, H7, H8,
H9, H10, H13, H14, J7,
J8, J9, J10, K7, K8, K9,
K10, K13, K14, L3, L4,
M13, M14, M15, N3, N4,
N5, N7, N9, N11, N13,
P2, P3, P5, P7, P9,P11,
P13, P14, R2, R14,
R15, R16, T1, T3, T7,
T10, T14, T16
VDD1
A5, A9, B10, C4, C8,
B4, C10, D3, D5, D7,
D9, D11, D14, E13, F3,
F4, F14, H3, H4, J13,
J14, L13, L14, M3, M4,
N6, N8, N10, N14, N15,
P4, P6, P8, P10, P15,
R4, R6, R8, R10, R12,
T5, T12
27, 48, 77,
100
Positive Power Supply VDD1. Nominally 3.3 Volt.
VDD2
IC0
C6, D6, J3, J4, N12, 14, 37, 64, Positive Power Supply VDD2. Nominally 1.8Volts.
P12, G13, G14
91
E15, F15, A12, A10, A6, 7, 41, 43, Internal Connection. These pins must be connected to VSS for
A2, B1, B3, C1, C2, D2, 65, 66, 67, normal operation.
E2, J2, K2, R1
68, 70, 71,
72, 86, 87,
88, 93, 94
NC A14, C15, D1, D15, E1, 24, 25, 26, No connection. These pins must be left open for normal
F1, G1, G15, H1, H15, 44, 45, 46, operation.
J1, J15, K1,
47, 49, 51,
K15,L1,L15,F2,L2 52, 53, 54,
55, 73, 74,
75, 76, 78,
79, 80, 82,
83, 84, 85,
89, 99, 50
IRQ R9
9 Interrupt Request (Open Drain Output). This output goes low
when an interrupt occurs in any channel. IRQ returns high when
all the interrupts have been read from the Interrupt FIFO
Register. A pull-up resistor (1K typical) is required at this output.
4 Zarlink Semiconductor Inc.

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ZL50233GD 전자부품, 판매, 대치품
Data Sheet
ZL50233
Each echo canceller contains the following main elements (see Figure 4).
• Adaptive Filter for estimating the echo channel
• Subtractor for cancelling the echo
• Double-Talk detector for disabling the filter adaptation during periods of double-talk
• Path Change detector for fast reconvergence on major echo path changes
• Instability Detector to combat instability in very low ERL environments
• Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection
• Disable Tone Detectors for detecting valid disable tones at send and receive path inputs
• Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals
• Offset Null filters for removing the DC component in PCM channels
• 0 to -12dB level adjusters at all signal ports
• Parallel controller interface compatible with Motorola microcontrollers
• PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding
Each echo canceller in the ZL50233 has four functional states: Mute, Bypass, Disable Adaptation and Enable
Adaptation. These are explained in the section entitled Echo Canceller Functional States.
Sin
(channel N)
µ/A-Law/ 0 to -12dB
Linear Level Adjust
Offset
Null
Disable Tone
Detector
Instability
Detector
Σ
Non-Linear
Processor
-
0 to -12dB
Level Adjust
Linear/
µ/A-Law
Microprocessor
Interface
MuteS
Double - Talk
Detector
Path Change
Detector
Narrow-Band
Detector
MuteR
Disable Tone
Detector
Sout
(channel N)
Rout
(channel N)
Linear/
µ/A-Law
0 to -12dB
Level Adjust
0 to -12dB
Level Adjust
Offset
Null
µ/A-Law/
Linear
Rin
(channel N)
Echo Canceller (N), where 0 < N < 3
Programmable Bypass
Figure 4 - Functional Block Diagram
1.1 Adaptive Filter
The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then
subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is
divided into two sections. Each section contains 512 taps providing 64ms of echo estimation. In Normal
configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay
configuration, both sections are cascaded to provide 128ms of echo estimation in channel A. In Back-to Back
configuration, the first section is used in the receive direction and the second section is used in the transmit
direction for the same channel.
Zarlink Semiconductor Inc.
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