ZL50233QCC Datasheet PDF - ETC
| Part Number | ZL50233QCC | |
| Description | 4 Channel Voice Echo Cancellor | |
| Manufacturers | ETC | |
| Logo |  |
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ZL50233
4 Channel Voice Echo Cancellor
Data Sheet
Features
• Independent multiple channels of echo
cancellation; from 4 channels of 64ms to 2
channels of 128ms with the ability to mix
channels at 128ms or 64ms in any combination
• Independent Power Down mode for each group of
2 channels for power management
• Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
• Passed AT&T voice quality testing for carrier
grade echo cancellers.
• Compatible to ST-BUS and GCI interfaces with
2Mb/s serial PCM data
• PCM coding, µ/A-Law ITU-T G.711 or sign
magnitude
• Per channel Fax/Modem G.164 2100Hz or G.165
2100Hz phase reversal Tone Disable
• Per channel echo canceller parameters control
• Transparent data transfer and mute
• Fast reconvergence on echo path changes
• Fully programmable convergence speeds
• Patented Advanced Non-Linear Processor with
high quality subjective performance
March 2003
Ordering Information
ZL50233/QCC 100-Pin LQFP
ZL50233/GDC 208-Ball LBGA
-40°C to +85°C
• Protection against narrow band signal divergence
and instability in high echo environments
• 0 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
• Offset nulling of all PCM channels
• 10 MHz or 20 MHz master clock operation
• 3.3 V I/O pads and 1.8V Logic core operation with
5-Volt tolerant inputs
• IEEE-1149.1 (JTAG) Test Access Port
• ZL50232, ZL50233, ZL50234 and ZL50235 have
same pinouts in both LQFP and LBGA packages
Applications
• Voice over IP network gateways
• Voice over ATM, Frame Relay
Rin
Sin
MCLK
Fsel
C4i
F0i
VDD1 (3.3V)
VSS
VDD2 (1.8V)
ODE
Serial
to
Parallel
PLL
Timing
Unit
Echo Canceller Pool
Group 0 Group 1
ECA/ECB ECA/ECB
Microprocessor Interface
Parallel
to
Serial
Note:
Refer to Figure 4
for Echo Canceller
block diagram
Test Port
Rout
Sout
RESET
DS CS R/W A10-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST
Figure 1 - ZL50233 Device Overview
1
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Data Sheet
ZL50233
Pin Description (continued)
PIN
Name
PIN #
208-Ball LBGA
100 PIN
LQFP
Description
DS R11
10 Data Strobe (Input). This active low input works in conjunction
with CS to enable the read and write operations.
CS R13
11 Chip Select (Input). This active low input is used by a
microprocessor to activate the microprocessor port.
R/W R5
12 Read/Write (Input). This input controls the direction of the data
bus lines (D7-D0) during a microprocessor access.
DTA
R7
13 Data Transfer Acknowledgment (Open Drain Output). This
active low output indicates that a data bus transfer is completed.
A pull-up resistor (1K typical) is required at this output.
D0..D7
T2,T4,T6,T8,T9,T11,
T13,T15
15, 16, 17, Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit
19, 20, 21, bidirectional data bus of the microprocessor port.
22, 23
A0..A10
P16,N16,M16,L16,K16,
J16,H16,G16,F16,E16,
D16
28, 29, 30, Address A0 to A10 (Input). These inputs provide the A10 - A0
31, 33, 34, address lines to the internal registers.
35, 36, 38,
39, 40
ODE
B13
57 Output Drive Enable (Input). This input pin is logically AND’d
with the ODE bit-6 of the Main Control Register. When both ODE
bit and ODE input pin are high, the Rout and Sout ST-BUS
outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout
and Sout ST-BUS outputs are high impedance.
Sout
A8
58 Send PCM Signal Output (Output). Port 1 TDM data output
streams. Sout pin outputs serial TDM data streams at 2.048 Mb/s
with 4 channels per stream.
Rout
B9
59 Receive PCM Signal Output (Output). Port 2 TDM data output
streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s
with 4 channels per stream.
Sin B11
60 Send PCM Signal Input (Input). Port 2 TDM data input streams.
Sin pin receives serial TDM data streams at 2.048 Mb/s with 4
channels per stream.
Rin B7
61 Receive PCM Signal Input (Input). Port 1 TDM data input
streams. Rin pin receives serial TDM data streams at 2.048 Mb/s
with 4 channels per stream.
F0i B5
62 Frame Pulse (Input). This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
C4i A4
63 Serial Clock (Input). 4.096 MHz serial clock for shifting data
in/out on the serial streams (Rin, Sin, Rout, Sout).
MCLK
G2
90 Master Clock (Input). Nominal 10MHz or 20MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
Zarlink Semiconductor Inc.
5
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| Information | Total 37 Pages | |
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