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X84256S8-1.8 데이터시트 PDF




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부품번호 X84256S8-1.8 기능
기능 UPort Saver EEPROM
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X84256S8-1.8 데이터시트, 핀배열, 회로
Preliminary
256K
X84256
µPort Saver EEPROM
MPSEEPROM
FEATURES
• Up to 10MHz data transfer rate
• 25ns Read Access Time
• Direct Interface to Microprocessors and
Microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low Power CMOS
—2.5V–5.5V and 5V ±10% Versions
—Standby Current Less than 1µA
—Active Current Less than 3mA
• Byte or Page Write Capable
—64-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 2ms
• High Reliability
—1,000,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Packages Options
—8, 16-Lead SOIC Packages
—14-Lead TSSOP Packages
—8-Lead XBGA Packages
DESCRIPTION
The µPort Saver memories need no serial ports or spe-
cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the µPort Saver uses
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the µPort Saver provides all
the serial benefits, such as low cost, low power, low volt-
age, and small package size while releasing I/Os for
more important uses.
The µPort Saver memory outputs data within 25ns of an
active read signal. This is less than the read access time
of most hosts and provides “no-wait-state” operation.
This prevents bottlenecks on the bus. With rates to 10
MHz, the µPort Saver supplies data faster than required
by most host read cycle specifications. This eliminates
the need for software NOPs.
The µPort Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This “bit serial” interface allows the
µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten-
tion is greater than 100 years.
BLOCK DIAGRAM
System Connection
Ports
Saved
µP
µC
DSP
ASIC
RISC
P0/CS
P1/CLK
P2/DI
P3/DO
A15
A0
D7
D0
OE
WE
Internal Block Diagram
MPS
WP H.V. GENERATION
TIMING & CONTROL
CE
COMMAND
I/O DECODE
OE
AND
CONTROL
LOGIC
WE
X
DEC
EEPROM
ARRAY
32K x 8
Y DECODE
DATA REGISTER
©Xicor, Inc. 1998 Patents Pending
4005 1 8/24/99 WW
1 Characteristics subject to change without notice




X84256S8-1.8 pdf, 반도체, 판매, 대치품
X84256
Preliminary
CE
OE
WE
I/O (IN)
I/O (OUT)
"0" A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
"1"
"0"
RESET
WHEN ACCESSING: X84256 ARRAY: A15=0
LOAD ADDRESS
LOAD DATA
START
NONVOLATILE
WRITE
Figure 2. Write Sequence
The nonvolatile write cycle is initiated by issuing a special
read/write “1”/read sequence. The first read cycle ends
the page load, then the write “1” followed by a read starts
the nonvolatile write cycle. The device recognizes 64-
byte pages (e.g., beginning at addresses XXXXXXXXX
000000 for X84256).
When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the first address on the
page, where data loading can continue. For this reason,
sending more than 512 consecutive data bits will result in
overwriting previous data.
result: I/O is LOW as long as a nonvolatile write cycle is
in progress, and l/O is HIGH when the nonvolatile write
cycle is done.
Low Power Operation
The device enters an idle state, which draws minimal
current when:
• an illegal sequence is entered. The following are the
more common illegal sequences:
—Read/Write/Write—any time
—Read/Write ‘1’—When writing the address or writ-
ing data.
A nonvolatile write cycle will not start if a partial or incom-
plete write sequence is issued. The internal write enable
latch is reset when the nonvolatile write cycle is com-
pleted and after an invalid write to prevent inadvertent
writes. Note that this sequence is fully static, with no spe-
cial timing restrictions. The processor is free to perform
other tasks on the bus whenever the chip enable pin
(CE) is HIGH.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be determined
at any time by simply reading the state of the l/O pin on
the device. This pin is read when OE and CE are LOW
and WE is HIGH. During a nonvolatile write cycle the l/O
pin is LOW. When the nonvolatile write cycle is complete,
the l/O pin goes HIGH. A reset sequence can also be
issued during a nonvolatile write cycle with the same
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
May change
from HIGH to
LOW
Don’t Care:
Changes
Allowed
N/A
Will change
from LOW to
HIGH
Will change
from HIGH to
LOW
Changing:
State Not
Known
Center Line
is High
Impedance
4

4페이지










X84256S8-1.8 전자부품, 판매, 대치품
X84256
Preliminary
CAPACITANCE
Symbol
CI/O(2)
CIN(2)
TA = +25°C, f = 1MHz, VCC = 5V
Parameter
Input/Output Capacitance
Input Capacitance
Max.
8
6
Units
pF
pF
Test Conditions
VI/O = 0V
VIN = 0V
Notes: (2) Periodically sampled, but not 100% tested.
POWER-UP TIMING
Symbol
tPUR(3)
tPUW(3)
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
2
5
Units
ms
ms
Notes: (3) Time delays required from the time the VCC is stable until the specific operation can be initiated.
Periodically sampled, but not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
VCC x 0.1 to VCC x 0.9
5ns
VCC x 0.5
EQUIVALENT A.C. LOAD CIRCUITS
5V
2.06K
OUTPUT
3.03K
30pF
3V
2.39K
OUTPUT
4.58K
30pF
2V
2.8K
OUTPUT
5.6K
30pF
7008 FRM F06
7008 FRM F07
7

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X84256S8-1.8

UPort Saver EEPROM

Xicor
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