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X84641S8-1.8 데이터시트 PDF




Xicor에서 제조한 전자 부품 X84641S8-1.8은 전자 산업 및 응용 분야에서
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부품번호 X84641S8-1.8 기능
기능 uPort Saver EEPROM
제조업체 Xicor
로고 Xicor 로고


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X84641S8-1.8 데이터시트, 핀배열, 회로
APPLICATION NOTE
A V A I LABLE
AN95 • AN103 • AN107
16K/64K/128K
X84161/641/129
µPort Saver EEPROM
MPSEEPROM
FEATURES
• Up to 10MHz data transfer rate
• 25ns Read Access Time
• Direct Interface to Microprocessors and
Microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low Power CMOS
—1.8V–3.6V, 2.5V–5.5V and 5V ±10% Versions
—Standby Current Less than 1µA
—Active Current Less than 1mA
• Byte or Page Write Capable
—32-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 2ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
DESCRIPTION
The µPort Saver memories need no serial ports or spe-
cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the µPort Saver uses
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the µPort Saver provides all
the serial benefits, such as low cost, low power, low volt-
age, and small package size while releasing I/Os for
more important uses.
The µPort Saver memory outputs data within 25ns of an
active read signal. This is less than the read access time
of most hosts and provides “no-wait-state” operation.
This prevents bottlenecks on the bus. With rates to 10
MHz, the µPort Saver supplies data faster than required
by most host read cycle specifications. This eliminates
the need for software NOPs.
The µPort Saver memories communicate over one line of
the data bus using a sequence of standard bus read and
write operations. This “bit serial” interface allows the
µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten-
tion is greater than 100 years.
BLOCK DIAGRAM
System Connection
Ports
Saved
µP
µC
DSP
ASIC
RISC
P0/CS
P1/CLK
P2/DI
P3/DO
A15
A0
D7
D0
OE
WE
©Xicor, Inc. 1994, 1997Patents Pending
7008-1.2 8/26/97 T2/C0/D0 SH
Internal Block Diagram
MPS
WP H.V. GENERATION
TIMING & CONTROL
CE
COMMAND
I/O DECODE
OE
AND
CONTROL
LOGIC
WE
X
DEC
EEPROM
ARRAY
16K x 8
8K x 8
2K x 8
Y DECODE
DATA REGISTER
7008 FRM F02.1
1 Characteristics subject to change without notice




X84641S8-1.8 pdf, 반도체, 판매, 대치품
X84161/641/129
Figure 2: Write Sequence
CE
OE
WE
I/O (IN)
I/O (OUT)
"0" A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
"1"
"0"
RESET
LOAD ADDRESS
WHEN ACCESSING: X84161 ARRAY: A15–A11=0
X84641 ARRAY: A15–A13=0
X84129 ARRAY: A15–A14=0
LOAD DATA
START
NONVOLATILE
WRITE
7008 FRM F05.1
Write Sequence
A nonvolatile write sequence consists of sending a reset
sequence, a 16-bit address, up to 32 bytes of data, and
then a special “start nonvolatile write cycle” command
sequence.
The reset sequence is issued first (as described in the
Reset Sequence section) to set an internal write enable
latch. The address is written serially by issuing 16
separate write cycles (WE and CE LOW, OE HIGH) to
the part without any read cycles between the writes. The
address is sent serially, most significant bit first, on the
l/O pin. Up to 32 bytes of data are written by issuing a
multiple of 8 write cycles. Again, no read cycles are
allowed between writes.
The nonvolatile write cycle is initiated by issuing a special
read/write “1”/read sequence. The first read cycle ends
the page load, then the write “1” followed by a read starts
the nonvolatile write cycle. The device recognizes 32-
byte pages (e.g., beginning at addresses XXXXXX00000
for X84161).
When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the first address on the
page, where data loading can continue. For this reason,
sending more than 256 consecutive data bits will result in
overwriting previous data.
A nonvolatile write cycle will not start if a partial or incom-
plete write sequence is issued. The internal write enable
latch is reset when the nonvolatile write cycle is com-
pleted and after an invalid write to prevent inadvertent
writes. Note that this sequence is fully static, with no spe-
cial timing restrictions. The processor is free to perform
other tasks on the bus whenever the chip enable pin (CE)
is HIGH.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be determined
at any time by simply reading the state of the l/O pin on
the device. This pin is read when OE and CE are LOW
and WE is HIGH. During a nonvolatile write cycle the l/O
pin is LOW. When the nonvolatile write cycle is complete,
the l/O pin goes HIGH. A reset sequence can also be
issued during a nonvolatile write cycle with the same
result: I/O is LOW as long as a nonvolatile write cycle is
in progress, and l/O is HIGH when the nonvolatile write
cycle is done.
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X84641S8-1.8 전자부품, 판매, 대치품
X84161/641/129
D.C. OPERATING CHARACTERISTICS (VCC = 2.5V to 5.5V)
(Over the recommended operating conditions, unless otherwise specified.)
Symbol
Parameter
Limits
Min.
Max.
Units
ICC1
VCC Supply Current (Read)
500 µA
ICC2
ISB1
ILI
ILO
VlL(1)
VIH(1)
VOL
VOH
VCC Supply Current (Write)
2
VCC Standby Current
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
1
10
10
–0.5
VCC x 0.3
VCC x 0.7 VCC + 0.5
0.4
VCC – 0.4
mA
µA
µA
µA
V
V
V
V
Test Conditions
OE = VIL, WE = VIH,
I/O = Open, CE clocking @ 5MHz
ICC During Nonvolatile Write Cycle
All Inputs at CMOS Levels
CE = VCC, Other Inputs = VCC or VSS
VIN = VSS to VCC
VOUT = VSS to VCC
IOL = 1mA, VCC = 3V
IOH = –400µA, VCC = 3V
7008 FRM T05.1
D.C. OPERATING CHARACTERISTICS (VCC = 1.8V to 3.6V)
(Over the recommended operating conditions, unless otherwise specified.)
Symbol
Parameter
Limits
Min.
Max.
Units
ICC1
VCC Supply Current (Read)
300 µA
ICC2
VCC Supply Current (Write)
1
ISB1
ILI
ILO
VlL(1)
VIH(1)
VOL
VOH
VCC Standby Current
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
1
10
10
–0.5
VCC x 0.3
VCC x 0.7 VCC + 0.5
0.4
VCC – 0.2
Notes: (1) VIL Min. and VIH Max. are for reference only and are not tested.
mA
µA
µA
µA
V
V
V
V
Test Conditions
OE = VIL, WE = VIH,
I/O = Open, CE clocking @ 3MHz
ICC During Nonvolatile Write Cycle
All Inputs at CMOS Levels
CE = VCC, Other Inputs = VCC or VSS
VIN = VSS to VCC
VOUT = VSS to VCC
IOL = 0.5mA, VCC = 2V
IOH = –250µA, VCC = 2V
7008 FRM T05.1
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X84641S8-1.8

uPort Saver EEPROM

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