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X9421 데이터시트 PDF




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부품번호 X9421 기능
기능 Single Digitally Controlled (XDCP) Potentiometer
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X9421 데이터시트, 핀배열, 회로
APPLICATION NOTES
AVAILABLE
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/SPI Bus
X9421
Single Digitally Controlled (XDCP) Potentiometer
FEATURES
• Single Voltage Potentiometer
• 64 Resistor Taps
• SPI Serial Interface for write, read, and transfer
operations of the potentiometer
Wiper Resistance, 150Typical at 5V
• 4 Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power Up.
• Standby Current < 5µA Max
• VCC : 2.7V to 5.5V Operation
2.5K, 10KEnd to End Resistance
• 100 yr. Data Retention
• Endurance: 100, 000 Data Changes per Bit per
Register
• 14-Lead TSSOP, 16-Lead SOIC
• Low Power CMOS
DESCRIPTION
The X9421 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four non-
volatile Data Registers that can be directly written to
and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
SPI
bus
interface
address
data
status
Bus
Interface &
Control
write
read
transfer
inc / dec
control
Power On Recall
Wiper Counter
Register (WCR)
Data Registers
4 Bytes
RH/VH
wiper
10K
64-taps
POT
VSS
RW/VW RL/VL
REV 1.1.6 8/1/02
www.xicor.com
Characteristics subject to change without notice. 1 of 21




X9421 pdf, 반도체, 판매, 대치품
X9421
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the potentiometer
and pot register are input on this pin. Data is latched by
the rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9421.
Chip Select (CS)
When CS is HIGH, the X9421 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9421, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A0)
The address input is used to set the least significant bit
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address
input in order to initiate communication with the X9421.
A maximum of 2 devices may occupy the SPI serial
bus.
Potentiometer Pins
VH/RH, VL/RL
The VH/RH and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
VW/RW
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers. Writing to the Wiper Counter
Register is not restricted.
System/Digital Supply (VCC)
VCC is the supply voltage for the system/digital section.
VSS is the system ground.
PRINCIPLES OF OPERATION
The X9421 is a highly integrated microcircuit
incorporating a resistor array and associated registers
and counter and the serial interface logic providing
direct communication between the host and the XDCP
potentiometer.
Serial Interface
The X9421 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9421 is comprised of one resistor array
containing 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
REV 1.1.6 8/1/02
www.xicor.com
Characteristics subject to change without notice. 4 of 21

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X9421 전자부품, 판매, 대치품
X9421
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
are defined as 0.
Two of the eight instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– XFR Data Register to Wiper Counter Register —This
instruction transfers the contents of one specified
Data Register to the Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between the potentiometer and one of its associated
registers.
Figure 4. Two-Byte Instruction Sequence
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9421; either between the host and one
of the Data Registers or directly between the host and
the WCR. These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the pot,
– Write Wiper Counter Register—change current wiper
position of the pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (tHIGH)
while SI is HIGH, the selected wiper will move one
resistor segment towards the VH/RH terminal. Similarly,
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the
VL/RL terminal. A detailed illustration of the sequence
and timing for this operation are shown in Figure 7 and
Figure 8.
CS
SCK
SI
0 1 0 1 1 1 0 A0 I3 I2 I1 I0 R1 R0 0 0
REV 1.1.6 8/1/02
www.xicor.com
Characteristics subject to change without notice. 7 of 21

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