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PDF X9430 Data sheet ( Hoja de datos )
| Número de pieza | X9430 | |
| Descripción | Dual Digitally Controlled Potentiometer (XDCP) with Operational Amplifier | |
| Fabricantes | Xicor | |
| Logotipo |  |
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X9430PPrrDNeoOulgciTN1aom-rORn8la8tEiDRamn8CcE-iOItagCNmoMrOTiuytMEMaraRETMbIlSeNlnEylcIDeLfNhEoCnDoDAirrEocmwDFannlOwRaStaRwrEulto.oNPpiinolpLEgtloAeWenrrCdstDEiClEM.PecSnEooItmNGetTer/NtsanScttiometer (XDCP™) with Operational Amplifier
FEATURES
• Two CMOS voltage operational amplifiers
• Two digitally controlled potentiometers
• Can be combined or used separately
• Amplifiers
—Low voltage operation
—V+/V- = ±2.7V to ±5.5V
—Rail-to-rail CMOS performance
—1MHz gain bandwidth product
• Digitally controlled potentiometer
—Dual 64 tap potentiometers
—Rtotal = 10k¾
—SPI serial interface
—VCC = 2.7V to 5.5V
DESCRIPTION
The X9430 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with
near rail-to-rail outputs. All pins for the two amplifiers
are brought out of the package to allow combining
them with the potentiometers or using them as com-
plete stand-alone amplifiers.
The digitally controlled potentiometers consist of a
series string of 63 polycrystalline resistors that behave
as standard integrated circuit resistors. The SPI serial
port, common to both pots, allows the user to program
the connection of the wiper output to any of the resistor
nodes in the series string. The wiper position is saved
in the on board E2 memory to allow for nonvolatile res-
toration of the wiper position.
A wide variety of applications can be implemented
using the potentiometers and the amplifiers. A typical appli-
cation is to implement the amplifier as a wiper buffer in
circuits that use the potentiometer as a voltage refer-
ence. The potentiometer can also be combined with
the amplifier yielding a digitally programmable gain
amplifier or programmable current source.
BLOCK DIAGRAM
HOLD
VCC
RW0 RH0 RL0
CS
SCK
SO
SI
A1
A0
Control and
Memory
WCR0
WCR1
WP VSS
RW1 RL1 RH1
V+
VNI0
+
– VOUT0
VINV0
VNI1
+
– VOUT1
VINV1
V–
REV 1.0 6/20/00
www.xicor.com
Characteristics subject to change without notice. 1 of 21
1 page  
X9430 – Preliminary Information
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
defined by the state of the A0-A1 input pins. The X9430
compares the serial data stream with the address input
state; a successful compare of both address bits is
required for the X9430 to successfully continue the
command sequence. The A0–A1 inputs can be actively
driven by CMOS input signals or tied to VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
Figure 1. Identification Byte Format
Device Type
Identifier
0 1 0 1 0 0 A1 A0
Device Address
Instruction Byte
The next byte sent to the X9430 contains the instruc-
tion and register pointer information. The four most sig-
nificant bits are the instruction. The next four bits point
to one of the WCRs of the two pots, and when applica-
ble, they point to one of four associated data registers.
The format is shown below in Figure 2.
Figure 2. Instruction Byte Format
Register
Select
I3 I2 I1 I0 R1 R0 0 P0
Instructions
WCR Select
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last bit (P0)
selects which one of the two potentiometers is to be
affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
The basic sequence of the two byte instructions is illus-
trated in Figure 3. These two-byte instructions
exchange data between a wiper counter register and
one of the four data registers associated with each. A
transfer from a data register to a wiper counter register
is essentially a write to a static RAM. The response of
the wiper to this action will be delayed tWRL. A transfer
from the wiper counter register (current wiper position)
to a data register is a write to nonvolatile memory and
takes a minimum of tWR to complete. The transfer can
occur between one of the two potentiometers and one
of its associated registers; or it may occur globally,
wherein the transfer occurs between both of the poten-
tiometers and one of their associated registers.
Five instructions require a three-byte sequence to com-
plete. These instructions transfer data between the
host and the X9430; either between the host and one
of the data registers or directly between the host and
the Wiper Counter and Registers. These instructions
are: 1) Read Wiper Counter Register, read the current
wiper position of the selected pot 2) Write Wiper
Counter Register, i.e. change current wiper position of
the selected pot; 3) Read Data Register, read the con-
tents of the selected nonvolatile register; 4) Write Data
Register, write a new value to the selected data register;
5)Read Status, returns the contents of the WIP bit which
indicates if an internal write cycle is in progress.
The sequence of these operations is shown in Figure 4
and Figure 5.
The final command is Increment/Decrement. It is differ-
ent from the other commands, because it’s length is
indeterminate. Once the command is issued, the mas-
ter can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (tHIGH)
while SI is HIGH, the selected wiper will move one
resistor segment towards the VH terminal. Similarly, for
each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the VL
terminal. A detailed illustration of the sequence and
timing for this operation are shown in Figure 6 and
Figure 7.
REV 1.0 6/20/00
www.xicor.com
Characteristics subject to change without notice. 5 of 21
5 Page 
X9430 – Preliminary Information
AMPLIFIER ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Symbol
VOS
TCVOS
IB
IOS
CMRR
PSRR
VCM
AV
VO
Parameter
Input Offset Voltage
Input Offset Voltage Temp.
Coefficient
Input bias current
Input offset current
Common mode
rejection ratio
Power supply
rejection ratio
Input common mode
voltage range
Large signal voltage gain
Output voltage swing
IO Output current
IS Supply current
GB Gain-bandwidth prod
SR Slew rate
ΦM Phase margin
Condition
V+/V- ±3V to ±5V
V+/V- ±3V to ±5V
V+/V- ±3V to ±5V
V+/V- ±3V to ±5V
VCM = -1V to +1V
V+/V- ±3V to ±5V
Tj = 25°C
VO = -1V to + 1V
V-
V+
V+/V- = ±5.5V
V+/V- = ±3.3V
V+/V- = ±5.0V
V+/V- = ±3.0V
RL = 100k, CL = 50pf
RL = 100k, CL = 50pf
RL = 100k,
CL = 50pf
Industrial
Commercial
Min. Typ. Max. Min. Typ. Max.
13
12
-10 -10
Unit
mV
µV/°C
50
25
70
50
25
70
pA
pA
dB
70 70
dB
V-
V+ V-
V+ V
30 50
30 50
V/mV
+0.1
+0.1
-.15
V
-.15 V
50 50 mA
30 30 mA
3 3 mA
1.5 1.5 mA
1.0 1.0 MHz
1.5 1.5 V/µsec
80 80 Deg.
V+ and V- (±5V to ±3V) are the amplifier power supplies. The amplifiers are specified with dual power supplies.
VCC and VSS are the logic supplies. All ratings are over the temperature range for the Industrial (-40 to + 85°C) and
Commercial (0 to 70°C) versions of the part unless specified differently.
REV 1.0 6/20/00
www.xicor.com
Characteristics subject to change without notice. 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet X9430.PDF ] | |
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