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XC1701 데이터시트 PDF




Xilinx에서 제조한 전자 부품 XC1701은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 XC1701 기능
기능 Serial Configuration PROMs
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XC1701 데이터시트, 핀배열, 회로
®
December 10, 1997 (Version 1.1)
0
XC1701L (3.3V), XC1701 (5.0V) and
XC17512L (3.3V)
Serial Configuration PROMs
0 5* Product Specification
Features
• On-chip address counter, incremented by each rising
edge on the clock input
• Simple interface to the FPGA; requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active Low)
for compatibility with different FPGA solutions
• Supports XC4000EX/XL fast configuration mode (15.0
MHz)
• Low-power CMOS Floating Gate process
• Available in 5 V and 3.3 V versions
• Available in compact plastic packages: 8-pin PDIP,
20-pin SOIC, and 20-pin PLCC.
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
Description
The XC1701L, XC1701 and XC17512L serial configuration
PROMs (SCPs) provide an easy-to-use, cost-effective
method for storing Xilinx FPGA configuration bitstreams.
When the FPGA is in master serial mode, it generates a
configuration clock that drives the SCP. A short access time
after the rising clock edge, data appears on the SCP DATA
output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
SCP. When the FPGA is in slave mode, the SCP and the
FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SCPs in this chain
are interconnected. All devices are compatible and can be
cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to the programmer.
VCC VPP GND
CE
RESET/
OE or
OE/
RESET
CLK
Address Counter
TC
EPROM
Cell
Matrix
Output
Figure 1: Simplified Block Diagram (does not show programming circuit)
CEO
OE
DATA
X3185
December 10, 1997 (Version 1.1)
5-1




XC1701 pdf, 반도체, 판매, 대치품
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs
* If Readback is
Activated, a
3.3-kResistor is
Required in
Series With M1
During Configuration
the 3.3 kM2 Pull-Down
Resistor Overcomes the
Internal Pull-Up,
but it Allows M2 to
be User I/O.
General-
Purpose
User I/O
Pins
* Vcc
M0 M1 PWRDWN
DOUT
M2
HDC
LDC
INIT
•••••
Other
I/O Pins
FPGA
OPTIONAL
Daisy-chained
FPGAs with
Different
Configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
Vcc
RESET
RESET
DIN
CCLK
D/P
INIT
VCC VPP
DATA
CLK
SCP
CE CEO
OE/RESET
DATA
CLK Cascaded
Serial
CE Memory
OE/RESET
(Low Resets the Address Pointer)
CCLK
(OUTPUT)
DIN
DOUT
(OUTPUT)
X8256
Figure 2: Master Serial Mode. The one-time-programmable Serial Configuration PROM supports automatic loading of
configuration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the
PROM data output one CCLK cycle before the FPGA I/Os become active.
5-4 December 10, 1997 (Version 1.1)

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XC1701 전자부품, 판매, 대치품
XC1701L/XC17512L
Absolute Maximum Ratings
Symbol
Description
Units
VCC Supply voltage relative to GND
-0.5 to +6.0
V
VPP Supply voltage relative to GND
-0.5 to +12.5
V
VIN Input voltage with respect to GND
-0.5 to VCC +0.5
V
VTS
TSTG
TSOL
Voltage applied to 3-state output
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in.)
-0.5 to VCC +0.5
-65 to +150
+260
V
°C
°C
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating
Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device
reliability.
Operating Conditions
Symbol
VCC
Description
Commercial
Supply voltage relative to GND 0°C to +70°C junction
Min Max Units
3.0 3.6
V
DC Characteristics Over Operating Condition
Symbol
Description
VIH High-level input voltage
VIL Low-level input voltage
VOH High-level output voltage (IOH = -4 mA)
VOL Low-level output voltage (IOL = +4 mA)
ICCA
Supply current, active mode
ICCS
Supply current, standby mode
IL Input or output leakage current
Note: During normal read operation VPP must be connected to VCC
Min
2.0
0
2.4
-10.0
Max
VCC
0.8
0.4
5.0
50.0
10.0
Units
V
V
V
V
mA
µA
µA
December 10, 1997 (Version 1.1)
5-7

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